JP2704324B2 - Synthesized signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synthesized signal generator for use in a device for generating a wideband signal.

[0002]

2. Description of the Related Art FIG. 3 shows the configuration of a conventional wideband synthesized signal generator. 3, reference numeral 20 denotes a reference signal oscillator, 21 denotes a first frequency divider for dividing the output of the reference signal oscillator 20, and 22 extracts a phase difference signal between the reference signal oscillator 20 and the voltage controlled oscillators 24, 25, and 26. A phase comparator; 23, an integrator for integrating the output of the phase comparator 22; 24, 25, 26, respectively, voltage-controlled oscillators having different bands; 27, a second frequency divider for dividing the output of the voltage-controlled oscillators 24, 25, 26; , 29, 30 are switches for switching the outputs of the voltage controlled oscillators 24, 25, 26,
Reference numeral 31 denotes a third frequency divider for dividing the outputs of the voltage controlled oscillators 24, 25, and 26; 32, a frequency data input terminal of the second frequency divider 27; and 33, an output terminal of the present apparatus.

Next, the operation of the above conventional example will be described.
The voltage controlled oscillator 24 outputs the output signal to the second frequency divider 2
After the frequency division by 7, the output of the reference signal oscillator 20 is compared in phase with the signal divided by the fixed first frequency divider 21 by the phase comparator 22, and the phase difference signal is integrated by the integrator 23. By feedback to the voltage controlled oscillator 24, the voltage controlled oscillator 24 is phase-synchronized with the reference signal oscillator 20.
Further, the output signal of the voltage controlled oscillator 24 is frequency-divided by the fixed third frequency divider 31 to obtain an output signal having a stable frequency. Further, by switching the voltage controlled oscillator 24 to the voltage controlled oscillators 25 and 26 having different bands using the switches 28, 29 and 30, a wide band output signal is obtained at the output terminal 33 of the present apparatus.

FIG. 4 shows an example of set values in the above conventional example. The reference signal of the reference signal oscillator 20 is 4 MHz, the frequency divider 21 is 1/10 fixed frequency divider, and the frequency divider 31 is 1/4 fixed frequency divider. Frequency, the oscillation frequency of the voltage controlled oscillator 24 is 60.0 MH
z to 75.6 MHz, the oscillation frequency of the voltage controlled oscillator 25 is 76.0 MHz to 95.6 MHz, and the voltage controlled oscillator 2
6 is 96.0 MHz to 120.0 MHz,
The frequency divider 27 is set to 1/15 by the frequency divider data input terminal 32.
0 to 1/300.

[0005] Voltage controlled oscillators 24, 25,
26 is switched using switches 28, 29, and 30 and the frequency division ratio of the second frequency divider 27 is arbitrarily set.
An output signal of 15 MHz to 30 MHz can be generated at the output terminal 33.

As described above, even the above-mentioned conventional synthesized signal generator can generate a wideband signal.

[0007]

However, in the above-mentioned conventional synthesized signal generating apparatus, a plurality of voltage controlled oscillators 24, 25,
26 and the switches 28, 29, and 30 have to be used, so that there are problems such as an increase in circuit scale and deterioration of signals due to the switches.

The present invention solves such a conventional problem, and the circuit scale is improved by securing a good phase noise characteristic by using one narrow band voltage controlled oscillator and a plurality of frequency dividers. It is an object of the present invention to provide a synthesized signal generation device capable of reducing a signal width and generating a wideband signal.

[0009]

According to the present invention, in order to achieve the above object, a first frequency divider is provided at a subsequent stage of a reference signal oscillator to make a frequency-divided output signal of the reference signal oscillator variable. A second frequency divider for synchronizing the phase with the reference signal oscillator and a third frequency divider for obtaining an output of a desired frequency are provided downstream of the narrow band voltage controlled oscillator .
The third frequency divider is configured such that the multiplication value of the frequency division ratio between the first frequency divider and the third frequency divider becomes constant for all frequencies of the output signal of the frequency divider. Are set so that the frequency division ratio of the first frequency divider increases and the frequency division ratio of the third frequency divider decreases sequentially as the frequency of the output signal increases.
The frequency dividing ratio of the frequency divider is variably controlled.

[0010]

Therefore, according to the present invention, a narrow band voltage controlled oscillator and first, second and third frequency dividers are controlled, and in particular, for all frequencies of the output signal of the third frequency divider. Thus, the first and second frequency dividers are sequentially set to the first and third frequency dividers so that the multiplied value of the frequency division ratio becomes constant and the frequency of the output signal of the third frequency divider increases. By setting the division ratio of the third divider to be large and setting the division ratio of the third divider to be small and variably controlling the division ratio of the second divider, a good phase can be obtained. There is an effect that the circuit scale can be reduced while ensuring noise characteristics, and a wideband output signal can be obtained.

[0011]

FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, 1 is a reference signal oscillator, 2 is a first frequency divider, 3 is a phase comparator that extracts a phase difference signal between the reference signal oscillator 1 and the voltage controlled oscillator 5, and 4 is an integrated output of the phase comparator 3. 5 is a narrow band voltage controlled oscillator, 6
Is a second frequency divider for dividing the output of the voltage controlled oscillator 5 and sending it to the phase comparator 3, and 7 is a third divider for dividing the output of the voltage controlled oscillator 5 to obtain a desired frequency signal. Divider,
8 is a frequency division data input terminal for setting frequency division data of the first frequency divider 2, 9 is a frequency division data input terminal for setting frequency division data of the second frequency divider 6, and 10 is A frequency division data input terminal 11 for setting frequency division data of the third frequency divider 7 is an output terminal of the apparatus. F ₁ is a reference signal oscillator 1 of the output signal, F ₂ is the first frequency divider 2 output signal, F ₃ is the output signal of the voltage controlled oscillator 5, F ₄ is the output signal of the second frequency divider 6, F ₅ is an output signal of the third frequency divider 7.

Next, the operation of the above embodiment will be described.
The output signal F ₁ of the reference signal oscillator 1 is divided by the first frequency divider 2 into 1 / N ₁ to obtain the output signal F ₂ . Further, the output signal F ₃ of the voltage controlled oscillator 5 is divided by the second frequency divider 6 into 1 / N ₂ to obtain the output signal F ₄ . Next, the output signal F ₄ and the output signal F ₂ are compared in phase by the phase comparator 3,
The phase difference signal is integrated by the integrator 4 and fed back to the voltage controlled oscillator 5. As a result, a stable output signal F ₃ synchronized with the reference signal oscillator 1 is obtained. Next, the output signal F ₃ of the voltage controlled oscillator 5 is divided by the frequency divider 7 into 1 / N ₃ to obtain a desired output signal F ₅ . In order to simplify the control, the multiplied value of the frequency division ratio of the first frequency divider 2 and the third frequency divider 7 is kept constant.

In the above embodiments, 15MHz～30MHz the frequency range of the output signal F _5, the frequency resolution 10
When the frequency is set to 0 kHz, the set value is determined so that the following equations are satisfied. F ₁ = 6 MHz (1) F ₃ = 6N ₂ N ₃ / N ₁ N ₃ (2) F ₅ = 6N ₂ / N ₁ N ₃ (3) 15 MHz ≦ F ₅ ≦ 30 MHz (4) N ₁ N ₃ = 60 (5) From equation (5), equations (2) and (3) are as follows. F ₃ = 0.1N ₂ N ₃ (6) F ₅ = 0.1N ₂ (7)

Therefore, the variable range of the output signal F ₅ is set to 1
To change from 5 MHz to 30 MHz, the frequency division ratio N ₂ must be 15
What is necessary is just to set it from 0 MHz to 300 MHz.

[0015] FIG. 2 shows an example of setting the numerical value to obtain a value of the output signal F _5. The reference signal of the reference signal oscillator 1 is 6 MHz, and the oscillation frequency of the voltage control oscillator 5 is 9
In the case of 0.0 MHz to 120.0 MHz, the output terminal 1
To the output signal F ₅ 1 and 15.0MHz~19.9MHz is, the frequency divider 2 a circumferential 1/10, the divider 7 1/6
And dividing, 20.0 MHz output signal F ₅ at the output terminal 11
In order to set the frequency to ２３23.9 MHz, the frequency divider 2 is frequency-divided by 1/12, the frequency divider 7 is frequency-divided by _５, and the output signal F ₅ at the output terminal 11 is 24.0 MHz to 30.0 MHz. , The frequency divider 2 is divided by 1/15 and the frequency divider 7 is divided by 1/4.
The frequency division ratio N ₂ of the frequency divider 6 is 1/150 from the above equation (7).
It is set to ~ 1/300.

Further, in order to obtain a good phase noise characteristic, it is necessary to narrow the frequency variable range of the voltage controlled oscillator 5, F ₅ is larger N ₃ when the 15 MHz, the formula (5) _{N 1} is reduced by. In addition, _{F 5}
There is the case of 30MHz to reduce the _{N 3, N 1} is increased by the above formula (5). That is, the first frequency divider 2 and the
3, the frequency of the output signal is higher.
As the frequency division ratio of the first frequency divider 2 increases,
The third frequency divider 5 is set so as to reduce the frequency division ratio.
It is.

Thus, according to the above embodiment, 90M
By controlling the narrow-band voltage-controlled oscillator 5 and the frequency dividers 2, 6, and 7 from 120 Hz to 120 MHz, it is possible to obtain a wide band output signal of 15 MHz to 30 MHz octave while securing good phase noise characteristics. it can. Also,
Since a plurality of voltage controlled oscillators and switches are not required as in the related art, the circuit scale can be reduced, and problems such as signal degradation due to the switches can be eliminated. In addition, the set value of the third frequency divider 7, the output signal F ₅ is a phase noise characteristic of the voltage controlled oscillator 5 12d
B (1/4 frequency division) can be improved by 15 dB (1/6 frequency division), and a phase noise characteristic equal to or better than 12 dB (fixed 1/4 frequency division) improvement in the conventional example can be secured.

[0018]

According to the present invention, as it is clear from the above examples, together constitute a single narrow band voltage controlled oscillator and three dividers to a predetermined connection relation, a third division of for all frequencies of the vessels of output <br/> force signals, as the multiplication value of the frequency division ratio of the first frequency divider and the third divider is constant, and the
As the frequency of the output signal of the third frequency divider becomes higher, the frequency division ratio of the first frequency divider is set to be larger and the frequency division ratio of the third frequency divider is set to be smaller in order. Since the frequency division ratio of the frequency divider is variably controlled, a wideband output signal can be obtained with a relatively simple configuration while maintaining good phase noise characteristics. Further, since a plurality of voltage controlled oscillators and switches are not required, the circuit scale can be reduced, and problems such as signal deterioration due to the switches can be eliminated.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a synthesized signal generator according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of set values in the device.

FIG. 3 is a schematic block diagram of a conventional synthesized signal generator.

FIG. 4 is a diagram showing an example of set values in the device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 reference signal oscillator 2 first frequency divider 3 phase comparator 4 integrator 5 voltage controlled oscillator 6 second frequency divider 7 third frequency divider 8, 9, and 10 frequency data input terminal 11 output terminal F _{1, F 2, F 3,} F 4, F 5 output signal

Claims (1)

(57) [Claims] A reference signal generator for generating a reference signal;
A first frequency divider for dividing the output signal of the reference signal oscillator, a narrow-band voltage-controlled oscillator for controlling the oscillation frequency,
A second frequency divider for dividing the output signal of the voltage controlled oscillator, a phase comparator for comparing the phases of the output signals of the first and second frequency dividers, and integrating the output signal of the phase comparator I
An integrator that sends a control voltage to the voltage-controlled oscillator after voltage conversion; and a third frequency divider that divides an output signal of the voltage-controlled oscillator . for all frequencies of the output signal, a first frequency divider and and as multiplied values of the frequency division ratio of the third divider is constant the third division of
The frequency divider of the first frequency divider is set to increase gradually and the frequency division ratio of the third frequency divider is set to decrease gradually as the frequency of the output signal of the frequency divider increases. Wherein the frequency division ratio is variably controlled to generate a wideband signal.