JPS6033456U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6033456U
JPS6033456U JP12596683U JP12596683U JPS6033456U JP S6033456 U JPS6033456 U JP S6033456U JP 12596683 U JP12596683 U JP 12596683U JP 12596683 U JP12596683 U JP 12596683U JP S6033456 U JPS6033456 U JP S6033456U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor device
external connection
semiconductor
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12596683U
Other languages
English (en)
Inventor
辻村　剛久
哲史 若林
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP12596683U priority Critical patent/JPS6033456U/ja
Publication of JPS6033456U publication Critical patent/JPS6033456U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来装置の断面図、第２図は従来装置・　　を
用いて回路基板に実装した場合の要部断面図、第３図は
本考案の一実施例の半導体装置の断面　　、。 図、第４図は本考案の一実施例の半導体装置に用いて回
路基板に実装した場合の要部断面図である。 図において１１はセラミック基板、１２は半導体素子、
１３は金属細線よりなるワイヤ、１４は外部接続用半田
パッド、１５はキャップ、１６は突起部を示す。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素子を収容するリードレスパッケージに設けられ
    た外部接続用半田付パッド上に半田付温度よりも高い融
    点を有する材料で形成された突起部を有してなることを
    特徴とする半導体装置。
JP12596683U 1983-08-12 1983-08-12 半導体装置 Pending JPS6033456U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12596683U JPS6033456U (ja) 1983-08-12 1983-08-12 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12596683U JPS6033456U (ja) 1983-08-12 1983-08-12 半導体装置

Publications (1)

Publication Number Publication Date
JPS6033456U true JPS6033456U (ja) 1985-03-07

Family

ID=30286595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12596683U Pending JPS6033456U (ja) 1983-08-12 1983-08-12 半導体装置

Country Status (1)

Country Link
JP (1) JPS6033456U (ja)

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