JPS6033306B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS6033306B2
JPS6033306B2 JP463179A JP463179A JPS6033306B2 JP S6033306 B2 JPS6033306 B2 JP S6033306B2 JP 463179 A JP463179 A JP 463179A JP 463179 A JP463179 A JP 463179A JP S6033306 B2 JPS6033306 B2 JP S6033306B2
Authority
JP
Japan
Prior art keywords
pattern
lift
metal film
photoresist
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP463179A
Other languages
Japanese (ja)
Other versions
JPS5596654A (en
Inventor
愛一郎 奈良
政夫 住吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP463179A priority Critical patent/JPS6033306B2/en
Publication of JPS5596654A publication Critical patent/JPS5596654A/en
Publication of JPS6033306B2 publication Critical patent/JPS6033306B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法において、リフトオフ法
による電極金属膜の形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming an electrode metal film by a lift-off method in a method of manufacturing a semiconductor device.

リフトオフ法というのは、写真製版技術において、微小
金属膜パターン又は絶縁膜パターンを形成する上で、特
にサブミクロンオーダのパターンを精度良く得る実用的
な方法である。
The lift-off method is a practical method for forming fine metal film patterns or insulating film patterns in photolithography, particularly for obtaining submicron-order patterns with high precision.

第1図を用いてこの方法について説明する。This method will be explained using FIG.

同図aにおいて、1は半導体基板で、2はスベーサとし
ての作用をするフオトレジスト膜である。場合によって
は、この膜厚を増やすために、フオトレジストに加えて
酸化膜(例えばSi02)を用いる場合もある。図bは
基板1の全面に、パターニングする材料例えば金属膜を
蒸着した状態を示している。
In FIG. 1A, 1 is a semiconductor substrate, and 2 is a photoresist film that acts as a substrate. In some cases, an oxide film (for example, Si02) may be used in addition to the photoresist to increase the film thickness. FIG. b shows a state in which a material to be patterned, such as a metal film, is deposited on the entire surface of the substrate 1.

図cはリフトオフ後の金属膜パターンを示している。こ
の場合、フオトレジスト膜2、及び金属膜3の厚みa,
bには実用上制約があり、b羊a でないとパターニングが良好にできない。
Figure c shows the metal film pattern after lift-off. In this case, the thickness a of the photoresist film 2 and the metal film 3,
There are practical restrictions on b, and good patterning cannot be achieved unless b is used.

一方、フオトレジスト膜2の種類として、サブミクロン
パターンの場合、解像度のすぐれたポジタィプフオトレ
ジスタ(商品名AZ−1350)が専ら使われているの
が現状で、その膜厚aは0.25〜0.40山mである
On the other hand, as for the type of photoresist film 2, in the case of submicron patterns, a positive type photoresist (product name AZ-1350) with excellent resolution is currently exclusively used, and its film thickness a is 0.25. ~0.40 mountain m.

これより厚ければ解像度が悪くなる傾向がある。したが
って、パターニングされる金属膜厚bは0.1〜0.2
rm程度である。
If it is thicker than this, the resolution tends to deteriorate. Therefore, the thickness b of the metal film to be patterned is 0.1 to 0.2
It is about rm.

これを例えばFETのゲート作製に応用した場合、ゲー
ト長1仏m,中30仏m,材質AIを使うと、ゲ−ト抵
抗は約400となる。これを下げることがFETデバイ
スのキーポイントである。本発明は例えば上述したゲー
ト抵抗を低減するために、金属膜厚を増やす新しい方法
を提案するものである。
For example, when this is applied to the fabrication of a FET gate, if the gate length is 1 French m, the medium is 30 French m, and the material is AI, the gate resistance will be about 400. Reducing this is the key point for FET devices. The present invention proposes a new method of increasing the metal film thickness, for example, in order to reduce the above-mentioned gate resistance.

次に、第2図を用いて本発明を詳細に説明する。Next, the present invention will be explained in detail using FIG.

第2図aは従来方法の第1図bにおいて、リフトオフし
ないで、さらにフオトレジストパターン21を重ね合わ
せたものである。
FIG. 2a shows the conventional method shown in FIG. 1b in which a photoresist pattern 21 is further superimposed without lift-off.

さらに、図bは再び金属膜31を全面蒸着した状態を示
している。しかるのち、リフトオフすると図cの様に厚
みの増した金属パターンが得られる。以上のべた方法が
、同一パターンのリフトオフを2回繰り返す方法と根本
的に異なるのは、第1層のフオトレジスト2をリフトオ
フしないで第2層のフオトレジスト21を形成するため
、半導体と接する部分のパターンがくずれないというこ
とである。つまり、従来の“2回りフトオフ法”はマス
ク合わせの精度を考慮に入れると、2回目の金属膜31
が1回目の金属膜21よりはみ出してパターンが太るこ
とは避けられない。ところがこの発明による方法はこの
様な可能性は全くない特徴がある。また、マスク合せが
多少ずれても、第1回目のパターンに第2回目のパター
ンが半分もしくは1′3以上重なっておればリフトオフ
は可能である。以上述べたように、本発明方法によって
半導体に接するパターン形状を変えることなく膜厚の厚
し、パターンのリフトオフが可能となって、特にFET
のゲート電極作成には大きな効果を発揮する。尚、本発
明はフオトレジスト以外のスベーサ及び金属膜以外の薄
膜材料のパターニングにも適用できることはいうまでも
なく、これらの厚み、形成条件は適宜決め得るものであ
る。
Furthermore, FIG. b shows a state in which the metal film 31 is deposited over the entire surface again. Thereafter, when lift-off is performed, a metal pattern with increased thickness is obtained as shown in Figure c. The above method is fundamentally different from the method of repeating lift-off of the same pattern twice because the second layer of photoresist 21 is formed without lifting off the first layer of photoresist 2. This means that the pattern does not change. In other words, the conventional "two-round lift-off method" takes into account the accuracy of mask alignment, and the second metal film 31
It is inevitable that the metal film 21 will protrude beyond the first metal film 21 and the pattern will become thicker. However, the method according to the present invention is characterized in that such a possibility does not exist at all. Further, even if the mask alignment is slightly misaligned, lift-off is possible if the second pattern overlaps the first pattern by half or 1'3 or more. As described above, the method of the present invention makes it possible to increase the thickness of the film without changing the shape of the pattern in contact with the semiconductor and to lift off the pattern.
It is highly effective for creating gate electrodes. It goes without saying that the present invention can be applied to patterning of substrates other than photoresists and thin film materials other than metal films, and the thickness and formation conditions thereof can be determined as appropriate.

また、この方法を2回以上重ねるリフトオフ法にも、こ
の発明は同様の原理で適用できることは明らかである。
It is clear that the present invention can also be applied to a lift-off method in which this method is repeated two or more times based on the same principle.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a〜cは従来のリフトオフ法を説明するための図
、第2図a〜cは本発明一実施例によるリフトオフ法を
説明するための図である。 図中、1は半導体基板、2はフオトレジスト、3は金属
膜、21,31は2層目のフオトレジスト,金属膜を示
す。尚、各図中同一符号は同一または相当部分を示す。
第1図 第2図
1A to 1C are diagrams for explaining a conventional lift-off method, and FIGS. 2A to 2C are diagrams for explaining a lift-off method according to an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a photoresist, 3 is a metal film, and 21 and 31 are the second layer photoresist and metal film. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1 半導体表面にパターニングされた第1層目スペーサ
層の上に加工されるべき薄膜材料を全面に成膜したのち
、スペーサを除去することなくさらに第1層目と同一パ
ターンの第2層目スペーサ層を重ね合わせてパターニン
グし、再び加工されるべき薄膜材料を成膜したのち、第
1層,第2層スペーサを同時に除去することによつて、
被加工薄膜の重ね合わされたパターンを形成することを
特徴とする半導体装置の製造方法。
1 After forming a thin film material to be processed on the entire surface of the first spacer layer patterned on the semiconductor surface, a second spacer layer with the same pattern as the first layer is further formed without removing the spacer. By stacking and patterning the layers, depositing the thin film material to be processed again, and simultaneously removing the first and second layer spacers,
A method for manufacturing a semiconductor device, comprising forming a pattern of overlapping thin films to be processed.
JP463179A 1979-01-17 1979-01-17 Manufacturing method of semiconductor device Expired JPS6033306B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP463179A JPS6033306B2 (en) 1979-01-17 1979-01-17 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP463179A JPS6033306B2 (en) 1979-01-17 1979-01-17 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5596654A JPS5596654A (en) 1980-07-23
JPS6033306B2 true JPS6033306B2 (en) 1985-08-02

Family

ID=11589359

Family Applications (1)

Application Number Title Priority Date Filing Date
JP463179A Expired JPS6033306B2 (en) 1979-01-17 1979-01-17 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6033306B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56130929A (en) * 1980-03-17 1981-10-14 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS5596654A (en) 1980-07-23

Similar Documents

Publication Publication Date Title
JPS63304644A (en) Method of forming via-hole
JPS6033306B2 (en) Manufacturing method of semiconductor device
JPH0748502B2 (en) Method for manufacturing semiconductor device
JP3030550B2 (en) Method for manufacturing analog semiconductor device
JP3348564B2 (en) Method for manufacturing dielectric capacitor
JPH07226396A (en) Pattern forming method
JP2504239B2 (en) Method for manufacturing semiconductor device
JPS58100434A (en) Method for forming spacer for lift off
JPH02213144A (en) Manufacture of semiconductor device
JP2533088B2 (en) Method of manufacturing thermal head
JPH0234195B2 (en)
JPS61263179A (en) Manufacture of josephson junction element
JPH05267356A (en) Semiconductor device and manufacture thereof
JPH01209726A (en) Method for forming electrode of semiconductor device
JPH0677254A (en) Formation of electrode
JPH04324673A (en) Formation of thin film resistance
JPH06151459A (en) Manufacture of thin-film transistor
JP2872298B2 (en) Method for manufacturing semiconductor device
JPS62299033A (en) Manufacture of semiconductor device
JPH0481876B2 (en)
JPH03239332A (en) Manufacture of semiconductor device
JPH0527969B2 (en)
JPH023926A (en) Forming method of wiring
JPH03159136A (en) Manufacture of semiconductor device
JPH0522380B2 (en)