JPS6032427A - General-purpose timing signal generating circuit - Google Patents

Abstract

PURPOSE:To generate a timing signal having an optional narrow pulse width and an optional phase from an input signal by giving a delay control signal and a selection control signal with a clock signal having a low frequency. CONSTITUTION:The delay time of a delay element array comprising cascade connection of delay elements D1, D2...Dn is varied by a delay control signal given externally. A pulse having an optional width delayed by an optional time from an input signal is outputted from a gate group comprising gates G12, G13... G1n in the unit of delay time of the delay element through the combination of each state output of the said array. A selection circuit 4 inputting an output of the gate group and each stage output of the delay element array and controlled selectively with a selection control signal given externally is provided. Further, the timing signal having an optional pulse width narrower than the pulse width of the input signal is generated in an optional timing by applying the delay control signal and the selection control signal to the circuit 4.

Description

TECHNICAL FIELD The present invention relates to a timing signal generation circuit used in a digital control device such as a data processing device.

Prior Art A conventional timing signal generation circuit is a circuit that generates a desired timing signal based on a basic clock generated by a clock generator or a clock signal f'7 obtained by dividing the basic clock. FIG. 1 is a block diagram showing an example of a conventional timing signal generation circuit, in which a high-speed clock with a frequency fit/2τ outputted from a clock generator 5 is manually supplied to a timing generation circuit 6.
is the pulse width τ at the required timing based on the clock
generates a timing pulse. In other words, in order to generate a timing pulse with a pulse width of l/2τ
A high-speed clock with a higher frequency is required.

For this reason, coupled with dramatic advances in semiconductor technology and integrated circuit technology, increasingly high-speed locks are becoming necessary. As a result, high-frequency noise is generated from the high-speed clock generation circuit, causing radio wave interference, and is causing a major social problem in terms of the 4R frequency band. Also, 1. In the conventional circuit described above, the pulse width and phase of the timing pulse are integral multiples of the clock k''r, and it is difficult to generate an optimal pulse 111111 signal with an optimal phase.

OBJECTS OF THE INVENTION The object 1-1 of the present invention is to solve the above-mentioned conventional drawbacks, and to provide an arbitrary f☆ phase with a clock of a low frequency.
An object of the present invention is to provide a general-purpose timing signal generation circuit capable of generating a timing signal with a pulse width of 11 times.

Structure of the Invention The timing signal generation circuit of the present invention comprises a delay element ~A L and I in which a plurality of stages of d delay elements r- are cascaded and whose delay times ν are changed by externally applied delay controllability. By combining the outputs of each stage of the delay element array, the delay time of the delay element is set to cH and is input (from No. 1). a selection circuit that inputs the output of the gate 41'' and the output of each stage of the delay element array and arbitrarily selects and outputs the output according to a selection control signal supplied from the outside, and provides the delay control signal and selection control signal. Accordingly, a timing signal having an arbitrary pulse width narrower than the pulse width of the input signal can be generated at an arbitrary timing.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

That is, delay elements DI, D2, . . .

An input signal do is input from the input signal terminal 2 to a delay element array in which Dn are connected in cascade. Delay time t of each delay element
is arbitrarily changed to f by the control signal r3c of Donobu 11J. The output of each stage of the delay element array A, d I, d
2. d3. . . . are respectively input to the gates G01°GO2, GO3, . Moreover, d2-dn are respectively K-1-G12. G13
．． −.

Each negation in Gln is ANDed with dl, and d3 to dn are gates 623 to G2n, respectively.
The logical product of each negation (-) and d2 is taken at . Similarly, the final stage output dn is the gate G
At (n-1), the negation signal and d (n-1) are ANDed. Human power signal d0.

11 Suki Chikanobu J +' Outputs d1 to dn of each stage of 7 rays
and output 5ol-si of case 1-G Ol-G On
n, G1-G12-Glr+ output s+2-sin
, outputs of gates G23 to G2n s 23- s 2n
, −:= , output s (n
-1) n is input to the selection circuit 4, and the selection circuit 4 selects any one of the input signals, one of 0:, or a combination thereof as an output signal according to the selection control signals AO to Am which are changed from the outside. Selectively output as V multiplier x. Therefore, it is possible to obtain a free timing signal corresponding to the extension control signal C and the selection control signals AO to An.

FIG. 3 is a time chart 1 showing the signals of various parts on the 2-actual male side, and the output s1 of the gate GI3 is the output signal X.
An example in which 3 is selected is shown below. As can be understood from the figure, an output signal with a pulse width of 11lt, which is much shorter than that of human power input + dθ, and a time t in the middle, is obtained, and the time t is By the signal, ffl
can be controlled. Therefore, the Kinio side does not require a high-speed clock to obtain a timing signal with a narrow pulse width, and has the advantage that high-speed clocks do not generate high-frequency noise.

In FIG. 2, by providing a plurality of input terminals f1 and delay control signals C, it is also possible to set different delay times for each stage of the delay element array. Also, depending on the configuration of the 1 selection circuit 4, it is possible to output multiple different timing signals.
It is F-noh.

FIG. 4 is a circuit diagram showing an embodiment in which the selection control signal input to the selection circuit 4 is fixed and a desired pattern is output. The signals of each part in this case are as shown in FIG. 5, and the output signal X has sol and s24 selected. Of course, by changing the fixing method, timing pulses of any other arbitrary pattern can be generated. What is important here is that the phase, pulse width, and pattern of the timing pulse can be set arbitrarily, and that a lower frequency signal is used as the source to generate the timing pulse. .

FIG. 6 is a block diagram showing another embodiment of the invention. In this case, digital data is stored in the data register 8, and the data read from the data register 8 is selected by the general-purpose timing signal generation circuit 9 according to the output of the control circuit 7. By supplying it as Am, it is possible to output the pulse I lane according to the content of the digital data (li line or 1.). 7, the selection control signals AO to Am output from the data register 8, and the output of the general-purpose timing signal generation circuit 9, rijX.

FIG. 8 shows yet another embodiment of the invention.

This is applied to preshift control in floppy disk controllers and rollers. The controller 10 is a commercially available floppy disk controller (L
SI D765AC (product name)), and the write signal W
DATA is the delay element r- of the general-purpose timing signal generation circuit 9.
By manually inputting the input signal terminal 2 to the array (No. 4 dO) and manually inputting the preshift control signals PSO, PSI to the general-purpose timing signal generation circuit 9 as the selected control signals AO to Am, as shown in Fig. t59. As such, the signal can be easily preshifted (1 I H),
) can be done. In this case, adjust the external resistance R and
The output signal
1 can be fine-tuned.

Effects of the Invention As described above, in the present invention, a low frequency clock is inputted to a delay element array, and the output and input signals of each stage of the delay element array are inputted to a group of gates. The configuration is such that pulses of various pulse widths are output at various timings, and these output signals and the outputs of each stage of the gate are arbitrarily selected and output by a selection circuit, and the delay time of the delay element is externally controlled. Since the selection of the selection circuit is controlled by an external selection control signal, a slow clock can be input to generate a timing signal of any pattern with a free pulse width. It is possible to generate and output at any phase. This circuit is suitable for integration and can provide a highly versatile timing signal generation circuit.

Furthermore, since the tree 1ijl path does not require a high J,';I wave clock, it is effective in reducing noise.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a conventional timing trust generation circuit, Fig. 2 is a small block diagram of an embodiment of the present invention, and Fig. 3 is a tight chart showing signals of various parts of the embodiment described above. 4 is a circuit diagram showing an embodiment in which the selection control signal is fixed; FIG. 5 is a time chart showing signals of each part of the embodiment described in section 2; and FIG. 6 is a circuit diagram showing another embodiment of the present invention. Block diagram, FIG. 7 is a time chart showing the output signals of the above embodiment, FIG. 8 is a block diagram of still another embodiment of the present invention, and FIG. 9 is a time chart showing the input/output signals thereof. It is. In the figure, ■ = delay control input terminal r, 2: human input signal terminal, 3: output signal terminal, 4: i3 selection circuit, 5: clock generator, 6: timing generation circuit, 7: control circuit, 8: data register , 9: Timing No. 6 generation circuit,
10: Floppy disk controller, D1-Dn:
Delay element, GOI-GOn, GI2-Gln, G2
3-G2n, G(n-1)n: Gate. Out Junjin 11 1 ni ki Co., Ltd. agent Patent attorney 1 / Living 111 Toshimune 6th d 7th day -- 'jt1k 8 reasons 9th day Shi Dingsa ": -, E-

Claims (1)

[Claims] The delay elements are controlled by a combination of a delay element f array in which a plurality of stages of delay elements whose delay time is varied by a delay control signal input from the outside are connected in series, and 115 horns at each stage of the delay element array. d extension 11ν1111 of m,
<k, the input signal is extended by an arbitrary time by 8, and the game 1-
J'1, the outputs of the group of gates I, and the outputs of each stage of the delay lines r-array and a are input, and the selection signal supplied from the outside is inputted. +R
It is equipped with a selection circuit that arbitrarily selects and outputs a nil control signal, and by applying the delay control signal and the selection IMI control signal, the pulse width is narrower than the width of the pulse width of the 14th to 50th pulse width. A general-purpose timing generator circuit No. 1 is characterized in that it generates a timing signal at a timing of 7a:.