JPS60246118A - Clock generating circuit - Google Patents

Abstract

PURPOSE:To adjust simply the length of logical ''0'' and logical ''1'' by giving logical ''1'' to the 1st input terminal of the 1st NAND gate, giving logical ''0'' to an input terminal of an inverting gate and connecting respectively the 1st and 2nd input terminals of the 2nd NAND gate and two of plural delay output terminals. CONSTITUTION:Explanation is made as to the adjustment that the period of logical ''0'' of an output waveform from an oscillator 1 is shorter than the normal value as shown in Fig. (a). A tap 10 and the 3rd connecting terminal 22, and the 6th connecting terminal and the 1st and 4th connecting terminals 20, 23 are connected respectively. Then, for example, a tap 11 and the 2nd connecting terminal 21 are connected. A signal [Fig. (d)] where the period of logical ''0'' is made longer is obtained at an output terminal 26 by ORing an output signal of the tap 10 [Fig. (b)] and an output signal of the tap 11 [Fig (c)] by the 1st three- input NAND gate 3. The period of logical ''0'' is made sequentially longer by changing sequentially the connected tap as taps 11, 12...19.

Description

[Detailed description of the invention] The present invention relates to a clock generation circuit.

In conventional clock generation circuits, there is no means for easily adjusting the length of the logic 'lO' and 0Ill periods of the clock signal obtained from this circuit.For this reason, in order to obtain a highly accurate circuit, it is necessary to The drawback is that expensive elements and strict parts selection are essential.

The object of the present invention is to eliminate the above-mentioned drawbacks and to provide a clock generation circuit in which the lengths of logic 1101 and logic 11'' can be easily adjusted.

The circuit of the present invention includes an oscillation means that outputs a rectangular wave signal with a period T having each level of logic "1" and oll, and a plurality of a delay means having a delay output terminal;
a first ONAN having at least first to third input terminals;
a D gate, an inverting gate having at least one input terminal and inverting the logic level of a signal input to the input terminal and outputting the inverted signal to a second input terminal of the NAND gate of the previous &J1; a second NAND gate having two input terminals, NANDing each signal input to the input terminal and outputting the NAND signal to the third input terminal of the first NAND gate;
ND gate, and when outputting from the first NAND gate without changing the interval length of each level of logic 1111 and "all" in the signal from the oscillation means, the input terminal of the inverting gate and the second NAN of
Applying logic ``On'' to the first input terminal of the D gate;
The second input terminal of the NAND gate has logic 9"l"? i:
One of the delayed output terminals of the number of plates is connected to the first input terminal of the first NAND gate, and the period of each level of logic I11'' and @0'1 in the signal from the oscillation means is determined. When changing the output length from the first NAND gate, a logic 111 is applied to the first input terminal of the first NAND gate and the first or second input terminal of the second ONAND gate. connecting the input terminal of the inverting gate and the second or first input terminal of the second NAND gate and two of the plurality of delayed output terminals, respectively; or the NA of the coffin 1;
Logic '111 is applied to the first input terminal of the NAND gate; logic 'lo1 is applied to the input terminal of the inverting gate; a+1 and the second input terminal of the second NAND gate; The two are connected respectively.

Next, the EJj of the present invention will be explained in detail with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, the temperature and water temperature are as follows:
The oscillator 1 is manufactured by the integration port 12i technology, and the total delay amount is less than or equal to the oscillation period A of the oscillator 1, and there are 10 predetermined delay amounts ``r1~Lo('I').

(=0) <T, <・<TIG) is obtained 10
a delay element 2 having adjustment taps lO~19;
3-man powered NAND gate 3, 62 1-man powered NAND gate 4, 2-man powered NAND gate 5 of M3, logic ``0''
Logic 10fi signal supply source 6 that outputs all level signals
and a logic “ll” which outputs a signal at the level of logic 1111.
'The signal supply source 7, the first connection terminal 20, the second connection terminal 21, the third connection terminal 22, and the fourth connection terminal 2
3, a fifth connection terminal 24 connected to the supply source 6, and a supply source ? It is composed of a sixth connection terminal 25 connected to VC and an output terminal 26. Next, a case will be described in which, for example, a clock with a duty ratio of 50t99 is obtained. Assuming that the output waveform of the oscillator 1 is a normal waveform with a duty ratio of 50 (@) as shown in FIG.
The third input terminal of the three-manpower NAND gate 3 and the connected first connection terminal 20 are connected. A jumper wire or the like is used as the connection means. Next, in order to disable the operation of the second one-manpower NAND gate 4 and the second two-manpower NAND gate 5, the fifth connection terminal 24 is connected to the second and third connection terminals 21 and 22. Then, the sixth connecting terminal 25 and the fourth connecting terminal 237 are connected by kasuri patterning. At this time, the waveform observed at the output terminal 26 is output "0" as shown in Section 21(b), and the logic Ill.
If the duty cycle is equal to the period of 50 (@), no fine adjustment is necessary.

Next, an explanation will be given of the adjustment when the output waveform from the oscillator l is shorter than the period of logic lOI or the normal value, as shown in FIG. 4+a). As shown in FIG. 3, the terminal 10 and the third connecting terminal 22. The sixth connection terminal 25 is connected to the first and fourth connection terminals 20 and 23, respectively. After this, for example, the tap 11 and the second connection terminal 21 are connected. By calculating the logical sum of the output signal of the tap io (FIG. 4(b)) and the output signal of the tap 11 (FIG. 4(C)) in the first three-man NAND gate 3, the logic 1l
A signal in which the period of O11 is lengthened (FIG. 2(d)) is obtained at the output terminal 26. Tap the tap to connect11.12・
・・・・・・．

19, the period of logic 1lOl can be sequentially lengthened. That is, by connecting an appropriate tap to the second connection terminal 21, the period of logic 0o11 can be adjusted to a normal value.

Furthermore, a case will be explained in which the output signal from the oscillator 1 has a logic lO1' period longer than the normal value, as shown in FIG. 6(a). As shown in FIG. 5, the fourth connection terminal 23 and the tap 10. The fifth connection terminal 24 and the second connection terminal 21. The sixth connection terminal and the first connection terminal are respectively connected. After that, for example, the tap 16 and the third connection terminal 22 are connected. Output signal of tap 10 (Fig. 6 (
b)) and the output signal of the tap 16 ((C) in the same figure) using the third two-man NAND gate 5,
A signal ((d) in the same figure) is obtained in which the period of the logic 101 is shortened. That is, by connecting an appropriate tap to the third connection terminal, the period of logic 10I+ can be adjusted to a normal value.

As described above, the present invention has the advantage that a lock signal can be generated with high accuracy.

[Brief explanation of drawings]

1, 3, and 5 are circuit diagrams for explaining one embodiment of the present invention, and the second factor, FIG. 4, and FIG. 6 are diagrams for explaining the present embodiment. In the figure, 1... oscillator, 2... delay element, 3 to 5... NAND gate, 6...
...Logic + lO1 signal source, 7...Logic 6
1" Signal supply source, 10-19...Tap, 20
~25...Connection terminal, 263 line/jumping Z reading 3rd figure 6th figure

Claims (1)

[Claims] An oscillation means for outputting a rectangular wave signal with a period T having each level of logic 111'' and o11, and a plurality of oscillation means for outputting a signal after delaying the signal from the oscillation means by a predetermined time, respectively. a delay means having a gamma delay output terminal; a first ONAND gate having at least first, second and third input terminals; and at least one input terminal, inverting the logic level of a signal input to the input terminal; an inverting gate that outputs the input signal to a second input terminal of the first NAND gate, and at least seven first and second input terminals, and performs a NAND operation on each signal input to the input terminals; a second ONAND gate that outputs the output to the third input terminal of the NAND gate of the oscillator; When outputting from the gate, the input terminal of the inverting gate and the first input terminal of the second NAND gate are supplied with VC logic JW, and the second input terminal of the second NAND gate is supplied with logic "111". One of the delay output terminals of the number is connected to the first input terminal of the first NAND gate, and the period length of each level of logic 1111 and nail O11 in the signal from the oscillation means is changed to When outputting from the first N A N D gate, the first
the first input terminal of the NAND gate and the second NAND gate of
Insert 'l' into the first or second input terminal of the AND gate.
? providing the input terminal of the inverting gate and the second ON
A, the second or first input terminal of the NAND gate and two of the plurality of delayed output terminals are respectively connected, or the first input terminal of the first NAND gate is connected to a logic 111 is applied to the input terminal of the inverting gate, and the first and second input terminals of the NAND gate of the power 2 are connected to the input terminal of the inverting gate. J! A clock generation circuit characterized in that two of the number of delay output terminals are connected to each other.