JPS62216414A - Delay circuit - Google Patents

Abstract

PURPOSE:To make a delay circuit into an integrated circuit by providing gate delay elements connected in multistages and semiconductor logic circuits, which take out delay signal outputs, at connection points of individual gate delay elements and controlling semiconductor logic circuits. CONSTITUTION:Semiconductor gate elements 1-1-1-n are used as delay elements to make it possible to integrate delay elements and to make it easy to join delay elements to another integrated circuit on demand. Semiconductor gate elements 1-1-1-n as delay elements are connected in multistages to generate many kinds of delay time. A desired phase delay is switched selectively by AND circuits 2-1-2-n provided in output parts of delay elements, and these selecting circuits consist of logic circuits suitable for integration, and delay circuits can be joined to another integrated circuit completely.

Description

[Detailed Description of the Invention] [Summary] In adjusting the amount of delay of a digital signal, gate delay elements connected in multiple stages and a semiconductor logic circuit for extracting a delayed signal output are provided at the connection point of each gate delay element, and the semiconductor logic The circuit is configured to output a phase-delayed signal by controlling the circuit, making it easy to integrate the delay circuit into an integrated circuit.

[Industrial application field]

The present invention relates to improvements in signal delay circuits, particularly digital signal delay circuits.

As electronic circuits are becoming more and more integrated using semiconductors, it is desirable that delay circuits used for signal phase adjustment have a structure that can be incorporated into such integrated circuits.

[Conventional technology]

Conventionally, delay circuits using coaxial lines as signal delay elements are known. However, such a configuration has limitations in miniaturization, and cannot be integrated into an integrated circuit.

[Problem that the invention seeks to solve]

The delay circuit must be able to be easily integrated with other integrated circuit parts in its configuration, and the integrated delay circuit must be able to easily adjust the phase delay time. The challenge is to provide the circuitry.

[Means for solving problems]

As shown in the principle diagram of the present invention in FIG. Connected to the AND circuits 2-1 to 2-n to which the control signal 3 is applied and the output section of each AND circuit, which are provided in order to extract a signal given the necessary delay time to each output point of the gate element. This problem is solved by the delay circuit of the present invention, which includes an OR circuit 4 constituting one delayed signal output section.

[Effect]

The present invention provides semiconductor gate elements 1-1 to 1 as delay elements.
By using -n, the delay element can be integrated, and if necessary, it can be easily integrated with other integrated circuits.

Further, by connecting the delay elements semiconductor gate elements 1-1 to 1-n in multiple stages, it is possible to generate various delay times. Further, the desired phase delay can be selectively switched by AND circuits 2-1 to 2-n provided at the output section of each delay element, and these selection circuits are composed of logic circuits suitable for integration. It allows the delay circuit to be completely integrated with other integrated circuits.

(Example〕 The details of the present invention will be explained below with reference to illustrated embodiments.

FIG. 2 is a circuit diagram showing an embodiment of the delay circuit of the present invention.

In the figure, 1-1 to 1-n are delay gate elements, 2-1 to 1-n are delay gate elements, and 2-1 to 1-n are delay gate elements.
2-n is an AND circuit, 3-1 to 3-n are control signals, 4 is an OR circuit, IN is a signal input section, and OUT is a signal output section.

A plurality of delay gate elements l-1-1-n are connected in cascade in multiple stages, and each gate provides a delay time of t1 to tn to a signal. The output section of each gate element is an AND circuit 2-1
~2-n is connected to one input.

The control signal 3 is connected to the other inputs of the AND circuits 2.1 to 2-n.
-1 to 3-n are supplied.

The OR circuit 4 is supplied with the output signals of the AND circuits 2-1 to 2-n, and the delayed signal is taken out from the output section OUT.

The operation of the delay circuit is as follows. Each time the signal applied to the input section IN passes through the delay gate element, tl, t
2. L3. ... is given, and the gate element 1-1
tl at the output of gate element 1-2, tl at the output of gate element 1-2
+t2. Thereafter, tl+t2+t3. ... is given a delay time.

Now, if the control signal 3-2 given to the AND circuit 2-2 is a high level signal and the control signals given to other AND circuits are low level, the input signal is passed through the AND circuit 2-2. is applied to the OR circuit 4.

This signal is transmitted to tl+ by gate elements 1-1 and 1-2.
A delay time of t2 is given.

Therefore, output section 0 (IT has tl+
An output signal delayed by t2 can be obtained.

FIG. 3 shows an NRZ/RZ using the delay circuit according to the present invention.
FIG. 4 is a block circuit diagram of one embodiment of the signal conversion circuit, and FIG. 4 is a waveform diagram at each part of the circuit shown in FIG.

In the figure, 5 is a flip-flop circuit, 6 is a delay circuit according to the present invention, and 7 is an AND circuit.

The NRZ signal i is applied to the D input terminal of the flip-flop circuit 5, and the NRZ signal iji having a pulse width matching the clock pulse interval is generated at the Q output terminal by the clock signal ii.

The output signal ii1 is the NRZ signal delayed by the flip-flop circuit element and is supplied to the AND circuit 7.

In order to obtain the RZ multiplied signal, the input signal Ni of the AND circuit 7
Since there is a phase delay, it is necessary to give a phase delay to the clock signal i+ and adjust the phase relationship between the two.

The phase adjustment is performed by delaying the clock signal ii by the delay circuit 6 so that the center of the clock pulse coincides with the center of the NRZ pulse, as shown in waveform diagrams iii and iv. In this way, an RZ multiplied signal can be obtained from the output of the AND circuit 7. The phase relationship of the waveform shown in 1iLiv must be adjusted according to the difference in bit rate, variation in element characteristics, etc. According to the delay circuit, this can be easily implemented by external adjustment.

〔Effect of the invention〕

According to the present invention, the amount of signal delay can be controlled by a digital control signal, and the delay circuit can be configured as an integrated circuit.

If an integrated delay circuit is integrated into a circuit part whose phase characteristics are affected by variations in internal elements, or which requires phase adjustment in order to make the circuit versatile for the pin rate used, it is possible to It is possible to provide a large-scale integrated circuit with good functions and characteristics1, and its effects are extremely large.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the delay circuit of the present invention. FIG. 3 shows an NRZ/RZ using the delay circuit according to the present invention.
This is a block circuit diagram of one embodiment of the signal conversion circuit, and FIG. 4 is a waveform diagram at each part of the circuit shown in FIG. In the figure, 1.1-1 to 1-n are delay gate elements, 2.2-1 to 2
-n is an AND circuit, 3.3-1 to 3-n are control signals, 4 is an OR circuit, 5 is a flip-flop circuit, 6 is a delay circuit, and 7 is an AND circuit. 1st Figure 3-1 3-2 ・−・−・・・・・・・
・・・・・・〜・・・−・ 3-nFigure 3

Claims (1)

[Claims] A multi-stage connected semiconductor gate element (
1), an AND circuit (2) in which the delayed signal of the gate element output section is supplied to one input section and a control signal (3) is supplied to the other input section, and a logic selected by the control signal; 1. A delay circuit comprising: an OR circuit (4) constituting one output section for a delayed signal outputted via a product circuit.