JPS6032366A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to use a material preferable as a gate electrode material which cannot be heretofore used for a gate electrode material by covering the second conductor after covering the first conductor. CONSTITUTION:An Au-Ge alloy is deposited on the entire surface of a GaAs substrate 11, thereby forming a source electrode 15 and a drain electrode 16. In this case, since gaps 17, 18 are formed between Si3N4 films 14 of the electrodes due to self-aligning with both side surfaces 13a, 13b of a photoresist 13. The electrodes 15, 16 are ohmically contacted with the substrate 11 by heating. An SiO2 film 20 is covered, with photoresists 21, 22 as masks the top 14a of the film 14 is exposed by etching with etchant of fluoric acid, and the film 14 is removed by etching with the etchant of fluoric acid. Pt is deposited on the overall surface, thereby forming a gate electrode 24 on the removed part 23. A problem that the electrode 24 is alloyed to the substrate 11 at the Pt in case of heat treatment can be entirely eliminated.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a method for manufacturing a semiconductor device.

BACKGROUND TECHNOLOGY AND PROBLEMS Conventionally, Schottky Goo) FIT is shown in Figures 1A to 1D.
It is manufactured by the method shown in the figure. That is, as shown in FIG. 1A, an M film (2) is deposited on the entire surface of a GaAs substrate (1) on which ions have been implanted for vT control in advance.
(by a vapor deposition method), and then a 7-photoresist is applied on top of the M film (2), followed by a predetermined patterning process to form a 7-photoresist (3). Next, 1B
As shown in the figure, using the photoresist (3) as a mask, the M film (2) is isotropically etched using, for example, a phosphoric acid-based etching solution to form a gate electrode (4). Next, in the state shown in FIG. 1B, GaAs
Depositing Au-Ge alloy on the entire surface of the substrate (1)
Finally, a source electrode (5) and a drain electrode (6) are formed. In addition, during the vapor deposition of the Au-Ge alloy, as a result of being self-aligned by both side surfaces (3a)' (3b) of the photoresist (3), it is aligned with each of the source electrode (5) and drain electrode (6). Between the gate electrode (4) and the gate electrode (4), there is a Ga of 7 photoresist (3) from the gate electrode (4).
Gaps (7) and (8) are formed with lengths approximately equivalent to #1 of the amount of protrusion in the direction parallel to the As substrate (1). Next, 1C
In the state shown in the figure, the photoresist (3) was
The Au--Ge alloy film (9) formed on the photoresist (3) during the Ge alloy vapor deposition is removed together with the lift-off method. After this, the GaAs substrate (1) was
The source electrode (5) and drain electrode (6) are heated to about 0°C near the respective interfaces between the source electrode (5) and drain electrode (6) and the GaAs substrate (1). By alloying the constituent Au-Ge alloy and the GaAs substrate (1) with each other, the source electrode (5) and the drain electrode (6) are formed on the GaAs substrate (1).
The Schottky Goo FET is completed by making ohmic contact with the Schottky Goo FET as shown in FIG. 1D.

The Schottky gate FET manufactured by the method described above has the following drawbacks. In other words, this Schottky
The threshold voltage VT of the FET is determined mainly by the above-mentioned ion implantation conditions for T control, variations in this ion implantation process, and the GaAs substrate used (1
), it is difficult to control VT to a predetermined value, and therefore it is difficult to match VT between multiple Schottky gate FETs. Tonoto Seven uses Ti as the material for the gate electrode (4) instead of the base.
The same applies to the case where a three-layer metal of /P t /Au is used.

The above-mentioned drawbacks can be eliminated by using Pt instead of M as the material for the gate electrode (4). This is because Pt is a GaAs substrate (1) at a relatively low temperature.
In order to form an alloy with
This is because the height of the channel formed in the aAs substrate (1) can be controlled, and therefore VT can be controlled to a predetermined value.

However, in the method shown in FIGS. 1A to 1D, pt cannot be used as the material for the gate electrode (4). This is because in the above method, the source electrode (5) and drain electrode (6) are formed after forming the gate electrode (4). During the heat treatment described above to make ohmic contact with the GaAs substrate (1),
Pt and GaAs substrate (1) constituting the gate electrode (4)
This is because J) VT changes significantly due to alloying with J), making it difficult to control VT to a predetermined value.

OBJECTS OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that allows use of materials that could not be used conventionally as gate electrode materials.

Summary of the Invention A method for manufacturing a semiconductor device according to the present invention includes the steps of: forming a mask on the semiconductor substrate, the mask having a protrusion extending in a direction parallel to the semiconductor substrate on the semiconductor substrate; a step of forming a first conductor on the semiconductor substrate; a step of forming a coating film covering the mask and the first conductor on the semiconductor substrate; a step of etching the above-mentioned coating film so as to form a covering film; a step of removing the above-mentioned mask by selectively etching through the above-mentioned opening; and forming an M2 conductor corresponding to the removed portion. We are trying to have a process for each. By doing this, it is possible to use a material suitable for a gate electrode material, which could not be used conventionally, as a gate electrode material.

EXAMPLES Hereinafter, examples of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

FIGS. 2A to 2J are process diagrams for explaining a first embodiment of the method for manufacturing a semiconductor device according to the present invention. The steps will be explained in the order of steps starting from FIG. 2A.

As shown in FIG. 2A, first, an 813N4 film α2 having a thickness of about 1 μm is deposited on the entire surface of a GaAs substrate aυ by the OVD method. Next, a photoresist (13) having a width of about 1.5 μm is formed by coating a photoresist on this Si3N4 film (t2) and performing predetermined patterning. Next, as shown in FIG. 2B, photoresist 0
Using the 5i5N4 film as a mask, the 5i5N4 film (1) is isotropically etched by a wet etching method using a phosphoric acid-based etching solution to form a 5i5N4 film with a width of about 1 μm. In the state shown in FIG. 2A, for example, anisotropic etching is performed using a reactive ion etching method to leave a 5i5N4 film with the same width as this photoresis) (13) under photoresis) Q31, and then reaction is performed. It can also be formed by performing isotropic etching using a plasma etching method.

Next, as shown in Fig. 2C, the Au-Ge alloy is made of GaAs.
A source electrode α9 and a drain electrode αe are formed by vapor deposition over the entire surface of the substrate 01). At this time, photoresist C1
3) are self-aligned by both side surfaces (13a) and (13b), so between the Si3N4 film (14) and (7) of the source electrode αω and drain electrode α6), and (
D G of photoresist 0th floor from Si3N4 film 04)
A gap αOat is formed with a length approximately equal to the protrusion amount of 0.25 μm in the direction parallel to the aAs substrate αυ. In addition, during the above vapor deposition, Au-Ge was also deposited on the photoresist α■.
Alloy film (1 cicada is formed.

Next, as shown in FIG. 2D, the photoresist N[31 is
After removing the u-Ge alloy film (along with l) by the lift-off method, the GaAs substrate αD is heated at a temperature of about 450°C for a predetermined period of time to form the source electrode α9 and the drain as described above. The electrode α6) is brought into ohmic contact with the GaAs substrate (11). Next, as shown in Figure 2B, 5
A 5i02 film (20) having a thickness of approximately 1 μm is deposited on the entire surface of the GaAs substrate αυ by the OVD method so as to cover the i5N4 film αa, the source electrode (15), and the drain electrode 06).

Next, as shown in Fig. 2F, a 7 photoresist Cυ (221) is formed by applying a photoresist on the 5i02 film (20) and turning it in a predetermined manner. Photoresist (
Using 2υ (221) as a mask, the 5i02 film (20) is etched with a hydrofluoric acid etching solution to expose the upper part (14a) of the Si3N4 film I.

Since the Si3N4 film I has etching resistance against hydrofluoric acid etching solution, it is not etched at all during the above etching. Note that the above 5i02 film (2t
), the upper part of the 5i5N4 film α(a) (
There is no problem even if 14a) is etched.

Next, as shown in the i2H diagram, the 5i5N4 film α exudate is removed by wet etching using a phosphoric acid etching solution. Note that 5i02 film (20a) (2
Since 0b) has etching resistance against phosphoric acid etching solution, it is not etched at all during the above etching. Next, by depositing PT on the entire surface in the state shown in Fig. 2H, S
A gate electrode (24) is placed on the removed part (c) of the i3N4 film αa.
form. During this vapor deposition, photoresist (2υ
(A Pt film (c) (to) is also formed on the two layers. After this, the photoresist (2υe molten metal) is removed together with the Pt film t2cm by the lift-off method, as shown in Fig. 2J. The Schottky gate FET is completed as shown.

In the first embodiment described above, after forming the source electrode α9 and the drain electrode (16) in the step shown in FIG. 2C, the gate electrode I2 is formed in the step shown in FIG. In the step shown in FIG. 2D, the source electrode a9 and the drain electrode (6) are made of GaAs.
The gate electrode (24) is not formed during the heat treatment described above to bring it into ohmic contact with the substrate 0υ, and therefore, during this heat treatment, the pt constituting the gate electrode (24) is alloyed with the GaAs substrate aυ. There is no problem mentioned above caused by the above-mentioned method.Therefore, Pt, which is preferable as a gate electrode material and which could not be used conventionally, can be used as a gate electrode material.Furthermore, in the state shown in FIG. By appropriately selecting conditions and performing heat treatment, the degree of alloying of Pt constituting the Sigut electrode (2→) and the GaAs substrate αD is controlled, thereby controlling VT to a predetermined value as described above. can do.

In the first embodiment described above, Pt is deposited on the entire surface in the state shown in Fig. 2H to form the gate electrode (two holes) as shown in the second construction drawing. The gate electrode (24) may be formed by.

That is, in Fig. 2H, 7otregi2) ρ9(221
After removing Pt, Pt is deposited on the entire surface, and then a photoresist is applied again on the Pt film formed by this deposition. After that, the photoresist remaining in the area where the gate electrode (24) is to be formed is removed by performing a predetermined turning process. A Sigut electrode (24) can be formed by etching the Pt film as a mask.

3A to 6E are process diagrams for explaining a second embodiment of the method for manufacturing a semiconductor device according to the present invention. The process will be explained in order from FIG. 3A below.

As shown in FIG. 6A, a source electrode made of a Si3N4 film (33, made of an Au-Ge alloy) is formed on a GaAs substrate (31) by a method similar to the steps shown in FIGS. 2A to 2E of the first embodiment. (to) and drain electrode c34), 5
After forming the t02 film 05), this 5i02 film (3!9
A Si3N4 film 06) is deposited thereon by the OVD method. Next, after coating a photoresist on this Si3N4 film 06), a predetermined patterning is performed to form a shift photoresist) 437) CIC3ω. Next, as shown in FIG. 3B, a photoresist C37) M (
Using 31 as a mask, the 5i5N4 film (36a) was etched by wet etching to form a 5i5N4 film (36a).
) (36b) (36c) are formed. Next, as shown in FIG. 60, the 5i5N4 film (36a) (36b
) Using (36c) as a mask, the 8i02 film 0!9 is etched by wet etching to expose the upper part (32a) of the Si3N4 film (34) and a part (34a) of the upper surface of the drain electrode 0a.

Next, the 5i5N4 film C3 is removed by wet etching as in the case of FIG. 2H. Note that during cono-etching, the 815N4 film <56a) (36b)
(36c) is also etched in a direction parallel to the GaAs substrate 0υ.

Next, as shown in FIG.
form υ. Note that during this vapor deposition, photoresist (3
7) Pt film (4a (4□□□(44
) is formed.

After this, photoresist (37) Oat (3!It
was removed by the lift-off method together with the Pt film (43 (44)), and then the Si3N4 film (56a) (36b
) (36c) is removed by wet etching to complete the Schottky gate FBTe as shown in FIG. 6E.

In the second embodiment described above, as in the first embodiment, Pt, which is preferable as a gate electrode material and which could not be used conventionally, can be used as the gate electrode material, and in the state shown in FIG. 5E. By performing appropriate heat treatment, F) VT can be controlled to a predetermined value. In addition, the gate electrode (40) and the wiring (41) can be formed at the same time by one-time vapor deposition.Also, as shown in FIG. 6E, the upper surface (40a) of the gate electrode (a) and the wiring (41) G of the top surface (41a)
Another advantage is that the heights from the aAs substrate 0a can be made almost the same.

In the first embodiment and the M2 embodiment described above, the 815 N4 film aaoa was formed at the position where the gate electrode was to be formed.
After removing the gate electrode (material) (4■
5i5N4 film aiea
If the gate electrodes (24) and (41) are formed with high precision in advance, the gate electrodes (24) and (41) can be formed with the same precision.

In addition, in the above-mentioned first and second embodiments, the second
As shown in Figure B, the protrusion is formed using photoresist α4, but the protrusion may be formed using other methods. For example, a canopy-like protrusion may be formed on the top of the 5i5N4 film Q41 itself by etching a suitable combination of anisotropic etching and isotropic etching as shown in FIG. 2A. Furthermore, in the first and second embodiments described above, -r is 5i5N4J[Q4)C
3′! After formation of lwo and ft-KSiO2J11r (2G
C11 formation Lt, lf, Si3N4 film (14) o'
a to 5i02 film, and 8i02 film (201 (3 to 8
It goes without saying that each film may be replaced with an iSN4 film, and the above two types of films may generally be constructed of 2s type films having selective etching properties. For example, Si3N
Instead of the four-layer film aaa'a, a high melting point metal such as W or Mo may be used.

Application Examples In the two embodiments described above, Ga is used as the semiconductor substrate.
Although an As substrate is used, the method for manufacturing a semiconductor device according to the present invention can also be applied to the case where other semiconductor substrates such as a Si substrate are used.

Effects of the Invention According to the method for manufacturing a semiconductor device according to the present invention, since the second conductor is deposited and formed after the first conductor is deposited, the process necessary for forming the first conductor is performed. The second conductor is not adversely affected. Therefore, a material suitable for a gate electrode material, which could not be used conventionally, can be used as a gate electrode material. Further, a mask having a protruding portion in a direction parallel to the semiconductor device on the top thereof is formed on the semiconductor substrate, and the first conductor is deposited on the semiconductor substrate using this mask.
Similar to conventional manufacturing methods, the first conductor can be formed by a self-alignment method.

Furthermore, since the second conductor is deposited to correspond to the portion where the mask has been removed, the gate electrode can be formed with high precision.

[Brief explanation of the drawing]

Figures 1A to 1D are process diagrams for explaining the conventional manufacturing method of Schottky gate FET, and Figures 2A to 2J.
6A to 6E are process diagrams for explaining a second embodiment of the semiconductor device manufacturing method according to the present invention. It is. In addition, in the symbols used in the drawings, (1) (11) Clυ=---GaAs substrate (4) H
...gate electrode (second conductor) (5) α9 (
C)... Source electrode (first conductor) (6) α6
1434)... Drain electrode (first conductor)
Photoresist (projection)
[4) (3a...5i5N+ m (mask) (2@05)...5i02 film (coating film) (c)... ...Removed part (4υ
・・・・・・・・・・・・Wiring. Agent Masaru Ueya Yoshio Tsuneko Toshiki Sugiura

Claims (1)

[Claims] a step of forming on the semiconductor substrate a mask having a protrusion in a direction parallel to the semiconductor substrate on the semiconductor substrate; a step of depositing and forming a first conductor on the semiconductor substrate using the mask; forming a coating film covering the mask and the first conductor on a semiconductor substrate; and etching the coating film so that an opening through which at least a portion of the mask is exposed is formed in the coating film. a step of removing the mask by selective etching through the opening, and a step of depositing and forming a second conductor corresponding to the removed portion. A method for manufacturing a semiconductor device.