JPS603218A - Transistor amplifier - Google Patents

Abstract

PURPOSE:To improve the linearity and high frequency characteristic of an amplifier by preventing a drain-source resistance of an MOSFET from fluctuating because of an input signal voltage. CONSTITUTION:A drain of the MOSFET1 is connected to a source of the MOS FET3, a gate of the MOSFET1 is connected to a gate of the MOSFET3 via a resistor 13 and a constant current source 18 is connected between the gate of the MOSFET3 and a power supply terminal 17. This constant current source 18 and the resistor 13 form a gate bias voltage of the enhancement MOSFET3. Further, the drain of the MOSFET3 is connected to the source of the enhancement MOSFET4, and an output terminal 15 is led out its connecting point. The drain and gate of the MOSFET4 are connected in common and its connecting point is connected to a power supply terminal 17 as a load. Then the drain of the MOSFET2 is connected to the power supply terminal 17.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a transistor amplifier suitable for application to, for example, an amplifier using a MOS FET.

[Background technology and problems thereof] In Fig. 1, 1 and 2 indicate MOS FETs whose sources are commonly connected, and this MOS FET 1
An input signal source 11 is differentially connected to the gates of and 2, and a constant current source 12 is connected to the source common connection point. Still, the source of MOSFET 4, whose drain and gate are commonly connected, is connected to the drain of one MOS FET 1, and
An output terminal 15 is led out from the drain of 1. Furthermore, the other MOSFET 2 train is connected to the power supply terminal 17.

In the above differential amplifier, the gain is Av, MOSFE
The transconductance of T1 and MOSFET4 is g1711. and gm4. If the resistance between the drain 7 and the source of the MOS FET 10 is rl, the gain is expressed as. In general, the mutual conductance of a MOS FET is gm, the drain current is ID, the gate-source voltage is Gs, the channel width is W, and the channel length is L.

Letting the gain constant be βeff, it is expressed as follows. Further, assuming that the drain-source voltage of the MOS FET is VDs and the early voltage is ■A, it is expressed as follows. Here, since the early voltage VA is a value unique to each MO3FET and ID is a constant current, the value of the drain-north resistance rd is equal to the drain-source voltage VDS
It will fluctuate depending on changes in.

In particular, when the channel length is shortened in order to increase the mutual conductance gln, the Early voltage decreases, the drain-source resistance rd decreases, and the influence of changes in the drain-source voltage VDS increases.

As mentioned above, the gain of the differential amplifier shown in FIG.
S FET transconductance gm and MOSFET
10 depends on the value of the drain-source resistance 1-1. Therefore, if the drain-source resistance r1 changes depending on the drain-source voltage VDS according to the input signal, a problem arises in that the linearity of the amplifier deteriorates.

Furthermore, the feedback capacitance existing between the gate and drain of the MOS FET 1 has the disadvantage of poor high frequency characteristics.

``Object of the Invention'' The object of the present invention is to provide a transistor amplifier with excellent linearity and good high frequency characteristics.

"Summary of the Invention" This invention provides an input signal source connected to the gate of a first transistor whose source is connected to a first reference potential point, and a drain of the first transistor connected to a source of a second transistor. A transistor characterized in that the gate of the first transistor is connected to the gate of the second transistor, and the drain of the second transistor is connected to a second reference potential point via a load. It's an amplifier.

"Embodiment" A first embodiment of the present invention will be described with reference to the drawings. In FIG. 2, reference numerals 1 and 2 indicate enhancement type MOSFETs whose sources are commonly connected, and an input signal source 11 is differentially connected to the gates of MOSFETs 1 and 2, and the source common connection point is A constant current source 12 is connected to constitute a differential amplifier.

The drain of MOS FET 1 is connected to the source of MOS FET 3, the gate of MOS FET 1 is connected to the gate of MOSFET 3 via resistor 13, and the MO
Constant current source 1 is connected between the gate of S FET 3 and power supply terminal 17.
8 is connected. This constant current source 18 and resistor 13 form a gate bias voltage of the enhancement type MOS FET 3. The drain of the MOS FET 3 is still connected to the source of the enhancement type MOS FET 4, and the output terminal 15 is led out from the connection point. M
The drain and gate of OS FET 4 are commonly connected,
The connection point is connected to the power supply terminal "17" and is used as a load.

The drain of MOS FET 2 constituting one differential amplifier is connected to power supply terminal 17 .

” In the configuration of the first embodiment of this invention of two series, MO
When a high level voltage is supplied to the gate of S FET 1 from the input signal source 11, the voltage at the drain of MOS FET I tends to decrease. On the other hand, a high level voltage in phase with that applied to MOS FET 1 by input signal source 11 is applied to MOS FET 1 via resistor 13.
, ET 3 is supplied to the gate of MOS FET
The voltage at the source of 3 is going to rise. MO3FE
Since the drain of T'1 and the source of MOSFET3 are connected to each other, the potential at the connection point (point A) is canceled by each other's voltage changes and does not fluctuate.
The drain-source voltage of ET1 does not change depending on the signal voltage.

The above relationship will be explained by showing a small signal equivalent circuit in FIG. In Figure 3, gml-5m4 is MOS FET1
It shows a transconductance of ~4, rl, f3 are MOS
Indicates the drain-source voltage of FETs 1 and 3,
vin and va indicate the input voltage and output voltage, respectively.
va indicates the voltage at point A. The voltage va at point A is third. In the 0 formula, Va=O when , 0
The formula is r3gm3- (1-3+ ;) gm+ = 0-■
Here, if ra>i, ra(gm3-gml) = 0...open・■・°・g
In3L: gml/curved surface■ The mutual conductance of MO5FET is determined by, so it is 0.
From the formula, when the relationship W, W (TJ:)3-(T)1......■ holds true, no signal voltage appears at point A, and nonlinearity due to drain-source resistance occurs. does not occur.

FIG. 4 shows a second embodiment of the invention. In the second embodiment, unlike the first embodiment, MOS FET
Connection point between gate 3 and resistor 13 and DC power supply terminal 19
A resistor 14 is connected between the two.

In case B, in order for the potential at point A to be unaffected by the signal voltage, if the resistance value of resistor 13 is R1 and the resistance value of resistor 14 is R2, then 2 (Rl + R2)gm3"F grn l °°−,,
, @ relationship must be satisfied.

FIG. 5 shows a third embodiment of the invention. In the third embodiment, a depression type MOS FET 3' is used as the MOS FET 3.

As in the first and second embodiments described above, unlike the case where the enhancement type MO5FET 3 is used, there is no need to supply a bias voltage, and the gate of MOS FET 1 and the gate of MOS FET 3' are directly connected. One side of the input signal source 11 is connected to the gate common connection point.

FIG. 6 shows a fourth embodiment of the invention. Similar to the third embodiment, this fourth embodiment is a depression type MO
This is an example in which 3FETs 3' and 5' are used. In this fourth embodiment, the other MOSFET 2 constituting the differential amplifier also has a MOSFET
The gate of MOS FET 2 and the gate of MOS FF, T s' are commonly connected, and the drain of MOS FET 2 is connected to the MOS FET.
The drain of MOS FET 5' is connected to the source of MOSFET 6 of the load, and the output terminal 16 is also led out from the connection point.

FIG. 7 shows a fifth embodiment of the invention. The fifth embodiment is an embodiment in which the present invention is applied to a single stage amplifier.

In Figure 7, both amplifier type MOS
The gate of FET 7 and the gate of MOS FET 8 are connected via a DC power supply 23, and the gate of MOSFET 7 is connected to an input terminal 20.

The drain of MOSFET7 is connected to the source of MOSFET8, and the drain of MOSFET80 is connected to the load M
It is connected to the source of the OS FET 9, and an output terminal 21 is led out from the connection point. The gate and drain of the MOS FET 9 are commonly connected, and this common connection point is connected to the power supply terminal 22.

FIG. 8 shows the depression type M in the fifth embodiment.
A sixth embodiment in which O3FET 8' is used will be shown. Unlike the fifth embodiment, the DC power supply 23 is not required,
The gate of MOS FET 7 and the gate of MOS FET 8' are directly connected.

The above-mentioned third part of this invention. 4th. In the fifth and sixth embodiments as well, it is possible to prevent the drain-source resistance from varying due to the signal voltage, and it is possible to improve the linearity of the amplifier.

Note that the MOS FFs, T4, and T9 serving as loads may be of either enhancement type or power compression type.

"Application Examples" This invention applies not only to MOS FETs using single crystal silicon, but also to amorphous silicon and polycondensate silicon.

The present invention can be similarly applied to MOS FETs using organic semiconductors. However, the present invention can also be applied to transistor amplifiers using bibolar transistors and junction FFEs.

[Effects of the Invention] According to the present invention, it is possible to prevent the drain-source resistance from varying depending on the input signal voltage, so that the linearity of the amplifier can be improved.

In fact, in this invention, since no signal voltage is applied to the drain of the transistor, feedback from the drain to the gate via the capacitance does not occur, and high frequency characteristics can be improved.

[Brief explanation of drawings]

Fig. 1 is a connection diagram of a conventional differential amplifier, Fig. 2 is a connection diagram of a first embodiment of this invention, and Fig. 3 is a connection diagram showing a small signal equivalent circuit of the first embodiment of this invention. , Figure 4, Figure 5,
FIGS. 6, 7 and 8 are the second embodiments of this invention. Third
．． 4th. It is a connection diagram of the 5th and 6th Example. 1 to 9・・・・・・Enhancement type MO3F
ET, 3'. 5', 8'...Depression type MO
5FET, 11...Input signal source, 12.18
・・・・・・・・・Constant current source, 13゜14 ・・・・・・
...Resistor, 15, 16.21...Output terminal, 17.22...Power terminal, 20.
...Input terminal. Agent Tomo Sugiura Figure 1 Figure 2 6 Figure 5 Figure 1 Figure 6 Figure 8

Claims (1)

[Claims] an input signal source is connected to the gate of a first transistor whose source is connected to a first reference potential point; a drain of the first transistor is connected to a source of a second transistor; A transistor amplifier characterized in that a gate of the transistor is connected to a gate of the second transistor, and a drain of the second transistor is connected to a second reference potential point via a load.