JPS6031275A - Transistor element - Google Patents

Abstract

PURPOSE:To facilitate the mounting of the emitter ground by a method wherein an emitter electrode is formed on the side of the element back surface, and a collector electrode and a base electrode on the side of the front surface. CONSTITUTION:A P type epitaxial layer 10 is formed as the base region B on a substrate 9 made N type. Next, an N<-> type epitaxial layer 13 serving as the collector region C is formed on the layer 10. Then, a P<+> diffusion source 14 is deposited on the layer 13. A base take-out region B' is formed by diffusing the diffusion source 14, and the layer 13 surrounded thereby is made as the collector region C. Besides, an N<+> diffusion source 11 is diffused and made as the emitter region E. An N<+> layer 15 is selectively diffused on the region C. Finally, the emitter electrode 16, collector electrode 18, and base electrode 19 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention particularly relates to a transistor element suitable for mounting with a common emitter.

As shown in Fig. 1, the current mainstream transistor element is based on selective thermal diffusion of P-type impurities onto the surface side of a substrate (1) of one conductivity type, for example, N-type, which becomes the collector region C. A base region B is formed by selectively thermally diffusing N-type impurities into the base region B, and an emitter region E is formed by selectively thermally diffusing N-type impurities into the base region B. A collector electrode (2) is formed on the back surface of the substrate (1) and The insulating film (3) on this surface is then selectively removed to form a base electrode (4).
This is a structure in which an emitter electrode (5) is formed. A transistor having such an NPN type transistor element (6) is suitable for mounting with a common collector, but may not be suitable for mounting with a common emitter, which is a recent trend.

For example, a transistor array circuit that obtains a high direct current amplification factor (hFE) uses the emitters of multiple transistors that are commonly grounded. In order to use the transistors in the Moreover, the characteristics were unfavorable. Therefore, in response to the increasing demand for common emitter grounding in transistor array circuits, there is a desire for a transistor element with an emitter electrode on the back side and a collector electrode and base electrode on the front side, but there is no suitable one yet. is the current situation.

Incidentally, it is possible in principle to use the collector having the structure shown in FIG. 1 as an emitter and the emitter as a collector. However, in this case, the base region is formed in the emitter/vine region by thermal impurity diffusion, and the collector region is formed in the base region by thermal impurity diffusion, so the impurity concentration in the collector region and base region inevitably becomes high. The C-B withstand voltage between them becomes small (about 20V at the most), and therefore, it is not possible to connect transistors in circuits that require a high C-B withstand voltage, such as transistor array circuits.

C.1 Objective of the Invention An object of the present invention is to provide a transistor element that solves the above-mentioned problems.

20 Construction of the Invention The present invention relates to a transistor element having a structure in which at least collector and base electrodes are provided on the surface side of the element, and a first conductivity type substrate serving as an emitter region and a base region of a different conductivity type are provided on the front side of the substrate serving as an emitter region. It is characterized in that an epitaxial layer and a second epitaxial layer serving as a collector region having the same conductivity type as the substrate are laminated, and at least a collector electrode and a base electrode are selectively formed on the second epitaxial layer. With such a structure, the collector region can be formed to have a desired thickness and a desired impurity concentration, and therefore characteristics that are equal to or better than conventional products can be obtained. In addition, since the emitter electrode is formed on the back side of the element without any problem in terms of characteristics, a transistor can be provided which is convenient for mounting because emitter common ground wiring, etc., as in a transistor array circuit, is easy.

E. Embodiment FIG. 2 shows a transistor element (8) which is an embodiment of the present invention.
), and its structure will be explained with reference to FIGS. 3 to 9. Note that the transistor element (8) will be described as a general NPN type.

First, a semiconductor substrate (9) having a thickness of about 200 μm as shown in FIG. 3 is prepared, and an N-type impurity is diffused into it at a relatively high concentration to make it N-type. Next, the thickness dimension T is approximately 10μ as shown in Figure 4 on the substrate (9).
A P-type first epitaxial layer (10) is formed as a base region B at m. Then, the first epitaxial layer (10
), as shown in FIG. 5, a 1 diffusion source (11) and a P- diffusion source (12) are sequentially and selectively deposited to form an adhesion.

Next, as shown in FIG.
An N-type second epitaxial layer (13), which will become the collector region C, is formed thereon to a thickness of about 40 to 100 μm. Then, as shown in FIG. 7, a P" diffusion source (14) is selectively deposited on the second epitaxial layer (13) in a portion facing the P+ diffusion source (12).

Thereafter, the whole is heated and the respective diffusion sources (11) and (12) are combined to form a base extraction region B', and the second epitaxial layer (13) surrounded by this is defined as a collector region C. In addition, a nitrogen diffusion source (11) is pushed into the first epitaxial layer (10) and diffused to directly connect the substrate (9) and the second epitaxial layer (13) to form an emitter region E.
shall be. Next, an N+ layer (15) is selectively diffused onto the collector region C to improve contact with metal. Further, in order to improve heat dissipation, the substrate (9) is polished from the back side to a desired position indicated by the broken line XX in FIG.

After that, as shown in FIG. 9, an emitter electrode (16) is formed on the back surface of the substrate (9), and a collector electrode (1B
) and the base electrode (19) are selectively formed, and then the ninth
By cutting along two broken lines Yl-Yl and Y2-Y in the figure, a plurality of transistor elements (8) shown in FIG. 2 can be obtained at once.

In the case of this transistor element (8), since the heath region B and the collector region C are formed by epitaxial growth layers, the impurity concentration can be set sufficiently low, and even if the emitter region E is N0, the concentration is relatively equivalent to Therefore, it is easy to increase the C-B breakdown voltage, and other characteristics (collector-emitter voltage VCE (SAT
) etc.) can also be obtained that is equivalent to or better than the general transistor element shown in FIG. In addition, it is easy to form the collector electrode (18) and base electrode (19) on the front side.
Such an electrode arrangement facilitates the construction of a transistor array circuit or the like.

In addition, although the emitter electrode (16) was formed on the back side of the element,
This is because the emitter region E surrounds the base region B and extends to the surface side, so that it is also possible to form the vine electrode on the surface side of the element.

Further, the present invention can be similarly applied to a PNP type transistor element.

As described in detail in Section 4 of the invention, the transistor element of the present invention has an emitter electrode on the back side of the element and a collector electrode and a base electrode on the front side of the element without any problems in terms of characteristics, so it can be used as an emitter-grounded mounting type. The present invention is particularly advantageous when applied to transistors constituting a ten transistor array circuit.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional transistor element, FIG. 2 is a sectional view showing an embodiment of the present invention, and FIGS. 3 to 9 are sectional views of a conventional transistor element.
FIG. 3 is a partial cross-sectional view at each step for explaining the manufacturing process of the transistor element shown in the figure. (9) - One substrate (10) - First epitaxial layer, (IIL - Second epitaxial layer, (18L - Collector electrode, (19) - Base electrode,
E - emitter region, c - collector region, B - base region. E Figure 6 Figure 8

Claims (1)

[Claims] (1) A first epitaxial layer serving as a base region of another conductivity type and a second epitaxial layer serving as a collector region having the same conductivity type as the substrate are laminated on one side of a substrate of one conductivity type serving as an emitter region, and 1. A transistor element comprising at least a collector electrode and a base electrode formed on two epitaxial layers.