JPS6031269A - Memory module - Google Patents
Memory moduleInfo
- Publication number
- JPS6031269A JPS6031269A JP58139269A JP13926983A JPS6031269A JP S6031269 A JPS6031269 A JP S6031269A JP 58139269 A JP58139269 A JP 58139269A JP 13926983 A JP13926983 A JP 13926983A JP S6031269 A JPS6031269 A JP S6031269A
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- memory
- memory module
- assembly
- damping
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 39
- 238000013016 damping Methods 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000007493 shaping process Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000007639 printing Methods 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 229910000859 α-Fe Inorganic materials 0.000 description 4
- 239000011324 bead Substances 0.000 description 3
- 241000257303 Hymenoptera Species 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
本発明はデータの記ｇ３読出しを行なうメモリモジュー
ルに関Ｊる。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory module for recording and reading data.
［発明の技術的背硝］
一般に、第１図に示ずＪ、うに、同軸ケーブル１より出
ツノを複数のメモリｌｃ２に分割して取り出す−場合に
、同軸クープル１側の出力インピーダンスとメモリＩＣ
２の人力インピーダンスとの不整合にｊ；り反則が起こ
り、出力波形の乱れが起こる場合があるが、この波形の
乱れを軽減するためにメモリＩＣ２の入力部にダンピン
グ抵抗３を挿入づることが行われ°Ｃいる。[Technical background of the invention] In general, when the output horn from the coaxial cable 1 is divided into a plurality of memories lc2 and taken out as shown in FIG. 1, the output impedance on the coaxial couple 1 side and the memory IC are
A mismatch with the human input impedance of the memory IC 2 may cause a violation and cause disturbance of the output waveform, but in order to reduce this disturbance of the waveform, it is possible to insert a damping resistor 3 into the input part of the memory IC 2. It is done °C.
［背景技術の問題点］
しかしながら、メモリモジュールに入力信号を入力部る
場合には、第２図に示７ように、このメモリモジュール
４の内部で各メモリＩＣ２の入力端子が共通に接続され
てしまっＣいるので、各メモリＩＣ２に、第１図に示り
Ｊ、うに、それぞれ固有のダンピング抵抗３を接続づる
ことができず、第２図に示すように、メモリモジコール
４全体としてダンピング抵抗３を１例外イーノ【ノする
ことしができなかった。[Problems with Background Art] However, when inputting an input signal to a memory module, the input terminals of each memory IC 2 are commonly connected inside the memory module 4, as shown in FIG. Since the damping resistor 3, as shown in FIG. I was unable to do 3 with one exception.
そのため、それぞれのメｔすＩＣ２に適合した適切なダ
ンピング抵抗を接続Ｊることができず、第１図のｈ法に
比べて十分なタンピング効果を得ることが難しがった。Therefore, it was not possible to connect an appropriate damping resistor suitable for each of the ICs 2, and it was difficult to obtain a sufficient damping effect compared to the method h shown in FIG.
［発明の目的コ
本発明はかがる従来の事情に対処してなされたちのＣ１
メモリモジュール内部にインピーダンス素子を接続し−
ｃ１十分なタンピング効果の冑られるメモリモジュール
を提供することを目的とづる。[Object of the Invention] The present invention has been made in response to the conventional circumstances.
Connect the impedance element inside the memory module.
c1 The purpose is to provide a memory module with sufficient tamping effect.
［発明の慨要］
すなわら本発明は、メモリＩＣの各入力端子にインピー
ダンス素子を接続し、該インピーダンス素子を前記メモ
リＩＣと同一のパッケージ内に収納しでなることを特徴
とＪるメモリモジコールＣある。[Summary of the Invention] In other words, the present invention provides a memory characterized in that an impedance element is connected to each input terminal of a memory IC, and the impedance element is housed in the same package as the memory IC. There is Mogicor C.
［発明の実施例］
以下本発明の詳細を図面に示り一実施例について説明す
る。[Embodiments of the Invention] Details of the present invention will be shown in the drawings and one embodiment will be described below.
第３図は本発明の一実施例を承り回路図である。FIG. 3 is a circuit diagram of an embodiment of the present invention.
図に８３いて符号６は、例えば６４ＫＸ４ピツｌ〜の記
憶容量を右りるダイナミックＲＡＭであり、この各ダイ
ナミックＲＡＭ６のアドレス入力端子、Ｒ４こＳ入力端
子、σＡｓ入力端子、ＷＲＩ−１−１入力端子、Ｄ Ｉ
Ｎ人ツノ端子にはそれぞれダンピング抵抗３３が接続さ
れている。各ダンピング抵抗３３は通常抵抗値が数十Ω
の値でしかも抵抗値の精度を必要とされないため、膜Ｉ
Ｃ技術にＪ：り印刷によってメモリモジュール５の基板
内に形成し得る。In the figure, numeral 6 at 83 is a dynamic RAM with a storage capacity of, for example, 64K x 4 bits, and each dynamic RAM 6 has an address input terminal, an R4 input terminal, an σAs input terminal, and a WRI-1-1 input. terminal, DI
A damping resistor 33 is connected to each of the N horn terminals. Each damping resistor 33 usually has a resistance value of several tens of Ω.
Since the value of the film I and the precision of the resistance value are not required
It can be formed in the substrate of the memory module 5 by printing according to C technology.
このようにメモリモジ二ノ、−ル５の基板の製造工程中
にダンピング抵抗３３を形成し得るので、メモリモジュ
ール５の基板製造後のアセンブリ工程は従来のアセンブ
リ工程とまったく同一でｊ′センブリ時間および製造コ
ストをほとんど変えることなく、各ダイナミックＲＡＭ
６の入力端子に必要なダンピング効果が得られるのぐあ
る。なお符号７．８．９．１０．１１はそれぞれダイナ
ミックＲＡＭ６の各アドレス入力端子、ＲＡ Ｓ入力端
子、ＣＡＳ入力端子、Ｗ ＲＩ −ｒ Ｅ 入力端子Ｊ
３ Ｊ： Ｕ Ｄ ＩＮ入力端子にダンピング抵抗３３
を介して接続される入力信号線である。また、符号１２
はダイナミックＲＡＭ６のＤ ｏｕ＋出力端子に接続さ
れた出力信号線を表ねり−０
このように本実施例においては、メモリモジュール５の
基板製造後のアセンブリ時１１ｉｉ１および！！！１造
コス］−をほとんど変えることなくダイナミックＲＡＭ
６の入力波形の整形がひき、ダイナミック［＜ＡＭ６の
誤動作の原因どなる人力波形のオーバーシュート、アン
ダーシュー１〜、リンギング等を大幅に減衰できる。Since the damping resistor 33 can be formed during the manufacturing process of the board of the memory module 5, the assembly process after manufacturing the board of the memory module 5 is exactly the same as the conventional assembly process, and the assembly time and manufacturing time are reduced. each dynamic RAM with almost no change in cost.
6 input terminals to provide the necessary damping effect. Note that the symbols 7, 8, 9, 10, and 11 are the address input terminals of the dynamic RAM 6, the RAS input terminal, the CAS input terminal, and the WRI-rE input terminal J, respectively.
3 J: Damping resistor 33 on the U D IN input terminal
This is an input signal line connected via the . Also, code 12
represents the output signal line connected to the Dou+ output terminal of the dynamic RAM 6 -0 Thus, in this embodiment, during assembly after manufacturing the memory module 5 board, 11ii1 and ! ! ! Dynamic RAM with almost no changes
The shaping of the input waveform of 6 is reduced, and the overshoot, undershoe, ringing, etc. of the manual waveform that causes malfunction of the dynamic [<AM6] can be significantly attenuated.
このようにして本実施例では、立ち上り時間および立ち
下がり時間が速い人力信号の波形整形に特に有効ひある
とどしに、メモリモジュール５の外部にタンピング抵抗
を外付けづる必要がなくなるのひ、実装が極め゛Ｃ容易
になるという効果も得られる。In this way, this embodiment is particularly effective in shaping the waveform of human input signals with fast rise and fall times, and eliminates the need to externally attach a tamping resistor to the outside of the memory module 5. Another advantage is that implementation becomes extremely easy.
第４図は本発明になるメモリモジュールの他の実施例を
示す斜視図である。図におい−Ｃ符号４はイの内部に図
示しないメモリＩｃを右Ｊるメモリモジュールであり、
このメ七りしジュール４の各リード端子１５にはフェラ
イ１へで作られたビーズ状のフェライトじ−ズ１４が接
続され、このフェライ１−ビーズ１４を介して図示しな
いメモリＩＣの各入力端子に入力信号が伝送される。FIG. 4 is a perspective view showing another embodiment of the memory module according to the present invention. In the figure, reference numeral 4 denotes a memory module with a memory Ic (not shown) inside it.
A bead-shaped ferrite bead 14 made from the ferrite 1 is connected to each lead terminal 15 of the ferrite module 4, and each input terminal of a memory IC (not shown) is connected via the ferrite 1 to the bead 14. The input signal is transmitted to
この）１ライトビーズ１４はインタフタンス成分と抵抗
成分とを有し、特にインタフタンス成分が支配的である
ため、入ツノ信号の人力レベルを減衰さけることなくダ
ンピング効果が１ｑられる。This) 1 light bead 14 has an intufftance component and a resistance component, and in particular, the intufftance component is dominant, so that a damping effect of 1q can be achieved without attenuating the human power level of the input horn signal.
［発明の効果］
以上述べたように本発明になるメモリモジ−７−ルにお
いＣは、メモリＩＣの各入力端子にインピーダンス素子
を接続し、このメモリＩＣと同一のパッケージ内に前記
インピータンス素子を収納して構成したので、メモリモ
ジュールの製造工程やコストを大きく変えることなく入
ノｊ信号波形の整形ができ、メモリＩＣの動作が安定と
なると同時に実装上も余分な外付は部品を必要としない
／、：め、極めて簡便に実装し得るという効果が青られ
る。[Effects of the Invention] As described above, in the memory module 7 of the present invention, an impedance element is connected to each input terminal of the memory IC, and the impedance element is placed in the same package as the memory IC. Because it is configured to be housed, the incoming signal waveform can be shaped without significantly changing the manufacturing process or cost of the memory module, and the operation of the memory IC is stable. At the same time, unnecessary external parts are not required for mounting. No/: The effect is that it can be implemented extremely easily.
第１図および第２図は従来のダンピング抵抗の接続方法
を示す回路図、第３図は本発明になるメモリモジュール
の一実施例を示Ｊ回路図、第４図は本発明になるメモリ
モジュール他の実施例を示す斜視図である。
１・・・・・・・・・・・・同軸ケーブル２・・・・・
・・・・・・・メモリＩＧ３．１３・・・ダンピング抵
抗
４．５・・・・・・メモリモジコール
６・・・・・・・・・・・・ダイナミック［＜ΔＭ１４
・・・・・・・・・・・・フエライ１〜ビーズ代理人弁
理士 須 山 ν［−
第１図
第３図
３
５1 and 2 are circuit diagrams showing a conventional damping resistor connection method, FIG. 3 is a circuit diagram showing an embodiment of a memory module according to the present invention, and FIG. 4 is a circuit diagram showing a memory module according to the present invention. FIG. 7 is a perspective view showing another embodiment. 1...Coaxial cable 2...
・・・・・・Memory IG3.13・・・Damping resistance 4.5・・・Memory module 6・・・・・・・・・Dynamic [<ΔM14
・・・・・・・・・・・・Fuerai 1 ~ Bees representative patent attorney Suyama ν [- Figure 1 Figure 3 3 5
Claims (1)
接続し、該インピーダンス素子を前記メモリＩＣと同一
のパッケージ内に収納し−〔なることを特徴とするメモ
リしジュール。(1) A memory module characterized in that an impedance element is connected to each input terminal of a memory IC, and the impedance element is housed in the same package as the memory IC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58139269A JPS6031269A (en) | 1983-07-29 | 1983-07-29 | Memory module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58139269A JPS6031269A (en) | 1983-07-29 | 1983-07-29 | Memory module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6031269A true JPS6031269A (en) | 1985-02-18 |
Family
ID=15241345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58139269A Pending JPS6031269A (en) | 1983-07-29 | 1983-07-29 | Memory module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6031269A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61290748A (en) * | 1985-06-19 | 1986-12-20 | Toshiba Corp | Memory module |
| JPS6297559U (en) * | 1985-12-09 | 1987-06-22 |
-
1983
- 1983-07-29 JP JP58139269A patent/JPS6031269A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61290748A (en) * | 1985-06-19 | 1986-12-20 | Toshiba Corp | Memory module |
| JPS6297559U (en) * | 1985-12-09 | 1987-06-22 |
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