JPS6031268A - Mis type semiconductor memory device - Google Patents

Abstract

PURPOSE:To accomplish the reduction of inter-element dimensions and the increase of the capacitance of a charge accumulated section at the same time by a method wherein grooves are formed in a semiconductor substrate, which are used as the insulation among the capacitance sections of a memory cell, and further the side surface section of the groove is utilized as the capacitor. CONSTITUTION:The grooves 20 are formed in the semiconductor substrate corresponding to the insulation region among the capacitance sections adjacent to each other of a memory device having one insulation gate type FET and the capacitor provided adjacent thereto on a semiconductor substrate as the unit of information. An impurity layer of the same conductivity type as the semiconductor substrate and higher concentration than the substrate is formed in the substrate at the bottom of this groove. An insulation film is formed in the grooves and on the surface of the substrate corresponding to the capacitance sections 21, and a conductive substance is deposited in the grooves and on the insulation film at the capacitance sections, being thus constructed as the capacitance electrode of the memory device. In this manner, the formation of the inversion layer on the groove side surface is enabled by diffusion of the impurity of reverse conductivity type to that of the substrate into the groove side surface, resulting in contribution to the increase of capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of an insulating part between a storage capacitor part and a storage capacitor part of a semiconductor memory device having a storage function in 1%.

The most widely used memory device today that uses insulated gate field effect transistors is the so-called "one-transistor type" memory device, which is composed of one transistor and a capacitor provided adjacent to the transistor. In this memory device, the gate of the transistor is connected to the word line, one of the source and drain diffusion layers is connected to the digit line, and the presence or absence of charge accumulated under one capacitor gate corresponds to inversion information.

When a MIS field effect transistor is used as a one-transistor type memory device, the capacitance Cs of the charge storage section is Cs
= ε8/l. Here, ε is the dielectric constant of the insulating film,
S is the electrical contact surface fIi1. of the capacitive part. [ is the thickness of the insulating film.

In recent years, as the integration of semiconductor devices has progressed, there has been a demand for miniaturization of elements. In miniaturizing a one-transistor type memory device, a decrease in the value of Cs must be avoided as much as possible in order to maintain ease of information determination and resistance to radiation. For this reason, in the conventional technology, the decrease in C8 was suppressed by reducing the thickness of the insulating film, but this method also does not always work because of the increase in pinhole density or the decrease in breakdown voltage due to thinning of the film. It was not a sufficient method.

The present invention forms a groove in a semiconductor substrate, uses the groove for insulation between capacitive parts of a memory cell, and further utilizes the side surfaces of the groove as a capacitor, thereby reducing the inter-element dimension and Cs. The aim is to simultaneously increase the The present invention has been developed in recent years.
The above effects have been made possible by introducing the newly devised device of the present invention into the developed inter-element insulation method for forming semiconductor elements. Insulating portions between capacitive portions of a memory cell are often covered with capacitive electrodes.

If the capacitor tin is not used with the capacitor tin grounded, by sufficiently increasing the substrate concentration of the insulating part, even if the insulating film thickness of the insulating part is thin, it is possible to prevent the ON L leakage current from flowing in the parasitic transistor. In this case, in order to form an inversion layer under the capacitor electrode, it is necessary to introduce impurities of the opposite conductivity type to the substrate surface to lower the circular value voltage. In the present invention, an inversion layer can be formed on the groove side surface by diffusing an impurity having a conductivity type opposite to that of the substrate on the groove side surface, thereby contributing to an increase in C8.

Next, embodiments of the present invention will be described using the drawings.

In this embodiment, a semiconductor device using an n-channel type silicon FET will be described.

In FIG. 1, a thick field oxide film 2 is formed on the p-type silicon base 1 by a normal selective oxidation method in the interelement insulation region other than the part that should become the insulation part between the storage cells. is formed. Next, as shown in Figure 2, after forming an oxide film 3 on the substrate, a photoresist 4 is deposited on the entire surface.
; 11+(circled part)'C or by electron beam exposure, an opening is formed in the photoresist 4 in a portion that is to be a region between the answering parts of the cell part. The oxide film 3 is used to maintain adhesion between the photoresist 4 and the substrate.

Next, as shown in FIG. 3, grooves are formed in the substrate by reactive ion etching. The gas used for etching is CCl4. It is preferable to use a chlorocarbon gas such as CCl3F or CCl2F2.

The frequency of high trapped wave power for inducing plasma is 13,
When the frequency is 56 MHz, the appropriate pressure is about 1 to 10 Pa. The etching speed of a silicon substrate depends on the electric power, but is between 0.1 and 1. 50 for power of about OW/Cni
Etching rates of the order of 0 to 2000 X/min are obtained. When forming deep grooves, it is difficult to obtain a sufficient etching rate selectivity between photoresist and cricon.
It is also possible to make the oxide film a thick oxide film grown in a vapor phase and use it as a spacer in etching. In this case, ij CF4 +H is used for etching the oxide film.
It is appropriate to use a two-system glue active ion etching.

Next, as shown in FIG. 4, mouth-type impurity 5 is ion-implanted into the bottom of the trench while leaving the photoresist 4.
A type impurity diffusion layer 6 is formed. When boron is used as an impurity, the appropriate energy is 50 to 150 KeV and the implantation amount is approximately 1013 to 1 O"/crl. Next,
As shown in FIG. 5, the photoresist 4 is removed and the entire surface is covered with n
An oxide film 7 doped with type impurities is formed. When phosphorus is used as an impurity, at a formation temperature of 400 to 500°C,
2000-30 under various conditions of mixing ratio of PH3/8jH4
By growing a phosphorus oxide film with a thickness of 9.00% by vapor phase growth and performing diffusion at a temperature of 900 to 1000°C, an n-type diffusion layer with a surface concentration of about 1018/m is formed as shown in Figure 6. You can get 8. Since the surface of the silicon substrate other than the groove portion is covered with an oxide film, n-type impurities are not diffused. Next, as shown in FIG. 7, the oxide film 7 doped with n-type impurities is removed by etching, a new insulating film 9 is formed, and a pattern is formed using photoresist 10 to form the capping portion. An n-type impurity layer 12 is formed by selectively implanting mouth-type impurity 11 into the surface of the silicon substrate. When arsenic is used as an impurity, the implantation amount is 10
12~1013/cr11 energy is 50~1501 (
Approximately eV is appropriate. The n-type impurity is diffused twice into the groove bottom, but in order to maintain sufficient insulation between elements, the amount of ion implantation shown in Figure 4 is set to a value higher than the amount of n-type impurity introduced. There is a need.

Next, as shown in m 8 +=, polycrystalline silicon 13 is deposited on the entire surface and buried inside the groove. When the groove width is about 1 μm1 and the groove depth is about 2 μm, the thickness of the polycrystalline silicon 13 needs to be about 1 μm or more.

The polycrystalline silicon 13 may be doped with a permeability impurity in advance, or may be doped with a conductive impurity by a thermal diffusion method after being deposited.

Next, as shown in FIG. 9, the polycrystalline silicon 13i is etched by normal grating etching using CFJ-based gas, leaving only the portion inside the groove.

Next, polycrystalline silicon 14 is deposited on the persimmon shown in the s fAL t o diagram, and a capacitor electrode and a gate electrode are formed by a photo-etching process. On Honjio's side.

Although a single layer of polycrystalline silicon was used, 2J@ polycrystalline silicon was used to form the capacitor electrode and the gate electrode separately, and the gate electrode was completely overlapped on the capacitor electrode to separate the capacitor and the channel region of the switching transistor. A directly connected structure, that is, a structure in which one of the source and drain in between is omitted, is also possible. Next, as shown in FIG. 11, □-type impurities 15, such as arsenic, are ion-implanted to form source and drain diffusion layers 16. Injection amount is 1015-1o16
/cdl, and the appropriate energy is about 50 to 150 KeV.

Next, as shown in FIG. 12, the polycrystalline silicon surface is covered with an insulating film by oxidation or vapor phase growth.

A contact opening is formed by a photoetching process,
Next, the remaining end is attached, and a conductive wiring layer is formed by a photo-etching process to complete the assembly.

FIG. 13 shows an example of a planar pattern of a memory cell to which the present invention is applied. The fish tube-shaped part shown by the oblique part in the upper right corner of the figure is the pattern of the part 2o, and three of the side surfaces of the cell capacitor part 21 can be used as a capacitor, so that C5 increases significantly. In FIG. 13, the area surrounded by a rectangle 0-O-0-Q and indicated by diagonal lines in the upper right corner is the gate electrode 22, and there is a gate electrode 22i on the channel region 23 in the center of the gate electrode 22iI. The field insulation film (lower right diagonal line) is provided on both sides (upper and lower sides in the drawing).
It extends partially over 24. The power supply 30 has its left and right edge lines 28 and 29 (l1Iil of o-o-o-o)
It is provided throughout the space between the holes (the diagonal lines are not shown because the drawing would be complicated). N-type bit spreading 7125
extends, and the part between this and the channel region 23 becomes one of the N-type source and drain regions 26 of the transistor, and the N-type source and drain regions are located between the channel region 23 and the capacitor section 21. The other area 27 is provided. If this other region 27 is used for the structure in which the gate electrical contact 22 and the capacitor electrode 30 are overlapped via the insulating film,
Can be omitted. A word line 31 made of aluminum as an upper layer extends perpendicularly to the pit line 25 and is connected to the gate electrode 22 through the entire contact hole 32.

Although the contact hole 31 is provided on the channel region in FIG. 13, it may of course be provided on the field insulating film. Note that in the 1m13 diagram, only one word line is shown to avoid complication, but it is possible that multiple word lines are provided in parallel and connected to each gate electrode via a contact hole. Of course.

Figure 14 shows the case where the capacitive part is 5 μm x 5 μm.
The relationship between groove depth and cell capacity is shown. If isolation between the regions is performed using a conventional insulation isolation method using a field oxide film pressed onto a semiconductor substrate, the cell capacitance is further reduced due to lateral encroachment of the field insulation film. on the other hand.

When the present invention is applied, it is possible to prevent the area of the capacitor portion from decreasing due to the biting of the upper portion. When the depth of the groove is 2 μm, a value of Cs approximately three times that of the conventional method is obtained, and even if the area of the pattern on the plane is reduced, an extremely large value of Cs can be obtained. Figure 16 shows the results of measuring leakage current noise between elements using the structure shown in Figure 15. In the case of a loop width of about 1 μm, it can be said that the leakage current value is a value that causes no practical problems if the potential of the capacitor electrode is grounded.

[Brief explanation of drawings]

111 to 12 are sectional views for explaining the present invention in detail. FIG. 13 is a plan view of an embodiment of the present invention. FIG. 14 is a diagram showing the effects of the present invention. FIG. 15 is a cross-sectional view of an experiment to determine the leakage current between cells in the present invention, and FIG. 16 is a diagram showing data obtained by FIG. 15. In the figure, 1... Silicon substrate, 2... Field oxide film, 3... Oxide film, 4... Photoresist, 5... ...n-type impurity ion, 6...
...P type diffusion layer, 7...N type impurity doped oxide film, 8...N type diffusion layer, 9...Insulating film, 10... ...Photoresist, 11...
...n3Jl impurity ion, 12...n-type diffusion layer, 13...polycrystalline silicon, 14...
・Polycrystalline silicon, 15...n-type impurity ion, 16...n-type diffusion layer, 17...metal wiring, 20...groove, 21... ...Cell capacitance section, 22...Gate electrode, 23...
Channel area, 24...Field 118
! Film, 25...Bit effect, 26...One region of source and drain, 27...
source, the other region of the drain, 28.29...
・・・The end of the planar shape of the capacitive connection is not shown, and the line 30...
... Capacitive electrode, 31 ... Powered line, 32 ...
...It's a contact. 1 ri＼ Agent Patent Attorney Uchihara Hi 1) Figure 1 Figure 7 Figure 3 1111 Lt Hi 84 85 Figure LIIJJM~/l Figure 13 0 / 2 34 5 Groove 1 Sa0tvrji f5 / 4 Figure 1 Tsuji otz 3 a V Valley (V) Figure 1b

Claims (1)

[Claims] In a storage device whose information unit is one insulated gate field effect transistor on a semiconductor substrate and a capacitance provided adjacent to it, it corresponds to the insulation area between the adjacent '8% parts of the IE storage device. A groove is formed in the semiconductor substrate at the bottom of the groove, and an impurity layer having the same conductivity type as the semi-circular substrate and having a higher concentration than the semi-circular substrate 4Fj is formed in the semiconductor substrate at the bottom of the groove. An insulating film is formed inside the trench and on the surface of the semiconductor substrate corresponding to the capacitive part, and a conductive material is deposited inside the trench and on the insulating film in the UN part to serve as the capacitive electrode of the storage device. (11-Featured MIa type semiconductor memory device.