JPS6031267B2 - voltage detection circuit - Google Patents

voltage detection circuit

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Publication number
JPS6031267B2
JPS6031267B2 JP16320278A JP16320278A JPS6031267B2 JP S6031267 B2 JPS6031267 B2 JP S6031267B2 JP 16320278 A JP16320278 A JP 16320278A JP 16320278 A JP16320278 A JP 16320278A JP S6031267 B2 JPS6031267 B2 JP S6031267B2
Authority
JP
Japan
Prior art keywords
voltage
current
carrying path
input
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16320278A
Other languages
Japanese (ja)
Other versions
JPS5587957A (en
Inventor
英男 杉山
秀春 手塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP16320278A priority Critical patent/JPS6031267B2/en
Publication of JPS5587957A publication Critical patent/JPS5587957A/en
Publication of JPS6031267B2 publication Critical patent/JPS6031267B2/en
Expired legal-status Critical Current

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Description

【発明の詳細な説明】 本発明は被検出電圧が広範囲に変動しても精度よく電圧
検出が行なえるようにした電圧検出回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage detection circuit capable of accurately detecting a voltage even if the voltage to be detected fluctuates over a wide range.

例えばサイン波のように時間と共にレベルが変動し、か
つそのピーク値がmV単位から数10Vまでの広範囲に
変動する入力電圧があって、この電圧のレベルがその時
のピーク値の所定%をこえたか否かを検出したい場合が
ある。
For example, if there is an input voltage whose level fluctuates over time like a sine wave, and whose peak value fluctuates over a wide range from mV units to several tens of volts, does the level of this voltage exceed a predetermined percentage of the peak value at that time? There are cases where it is desired to detect whether or not the

そして上記入力電圧が数10V程度と高い場合に、±数
%のノイズがのころことが予想されれば、上記低い電圧
から高い電圧までの広い範囲にわたり、上記電圧検出を
同一の検出回路で行なうことは極めて困難なことである
。本発明は上記実情に鑑みてなされたもので、被検出電
圧が広範囲にわたって変動し、またこれに或る程度のノ
イズがのっても、精度よく電圧検出が行ない得る電圧検
出回路を提供しようとするものである。
If the input voltage is as high as several tens of volts, and noise of ±several percent is expected to occur, the voltage detection is performed over a wide range from the low voltage to the high voltage using the same detection circuit. This is extremely difficult. The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a voltage detection circuit that can accurately detect voltage even if the voltage to be detected fluctuates over a wide range and even if a certain amount of noise is added to the detected voltage. It is something to do.

以下図面を参照して本発明の一実施例を説明する。An embodiment of the present invention will be described below with reference to the drawings.

第1図において1はサイン波等の外部入力信号Vinが
供給される入力端子であり、この端子1はアッテネータ
部2で抵抗Rx,R,、NPNトランジスタQ,のコレ
クタ、ェミツタを介して接地供給端子3に接続される。
トランジスタQ,のべ−スはオベアンプ4の出力様子に
接続され、コレクタはオベアンプ4の非反転入力端子(
‘‘十”様子)に接続され、基準電圧Vrefの供給端
子5はオベアンプ4の反転入力端ぐ一”端子)に接続さ
れる。抵抗Rx,R,間の接続端(ここの電圧をV,と
する)はオベアンプ6、コンパレータ7の“十”端子に
接続される。オベアンプ6の出力端はNPNトランジス
タQ2のべ−ス、エミツタ(ここの電圧をV2とする)
を介して自己の“一”端子に接続される。またオベアン
プ6の出力端はコンデンサC,を介して接地され、トラ
ンジスタQ2のェミッタは抵抗R2を介して接地される
。トランジスタQ2のコレクタは、カレントミラー回路
8のNPNトランジスタQ3,Q4のベース接続機及び
トランジスタQ3のコレクタに接続する。トランジスタ
Q3,Q4のェミッタは電源Vccの供給端子9に接続
し、トランジスタQ3,Q4のェミッタ及びコレクタ間
には定電流源10,11を接続する。トランジスタQの
コレクタはダイオードD,、抵抗R3を介して接地し、
ダイオードD,、抵抗R3間(ここの電圧をV3とする
)はコンパレータ7の“一”端子に接続する。コンパレ
ータ7の出力端はNPNトランジスタQ5,Q6のベー
スに接続し、このトランジスタ鴇のコレク夕はトランジ
スタQのコレクタに接続し、トランジスタQ6のコレク
タは出力端子12に接続し、トランジスタは、Q6のェ
ミツタは接地する。第2図aは第1図のアッテネータ部
2の具体例であり、抵抗R,の一端の電圧V4をV4=
Vrefとするものである。
In Fig. 1, 1 is an input terminal to which an external input signal Vin such as a sine wave is supplied, and this terminal 1 is connected to the ground via the collector and emitter of resistors Rx, R, and NPN transistor Q in an attenuator section 2. Connected to terminal 3.
The base of the transistor Q is connected to the output of the amplifier 4, and the collector is connected to the non-inverting input terminal of the amplifier 4 (
The reference voltage Vref supply terminal 5 is connected to the inverting input terminal of the amplifier 4. The connection terminal between the resistors Rx and R (the voltage here is assumed to be V) is connected to the "10" terminal of the oven amplifier 6 and the comparator 7. The output terminal of the OBE amplifier 6 is the base and emitter of the NPN transistor Q2 (the voltage here is assumed to be V2).
It is connected to its own “one” terminal via. Further, the output terminal of the obeamp 6 is grounded via a capacitor C, and the emitter of the transistor Q2 is grounded via a resistor R2. The collector of the transistor Q2 is connected to the base connections of the NPN transistors Q3 and Q4 of the current mirror circuit 8 and the collector of the transistor Q3. The emitters of the transistors Q3 and Q4 are connected to the supply terminal 9 of the power supply Vcc, and constant current sources 10 and 11 are connected between the emitters and collectors of the transistors Q3 and Q4. The collector of transistor Q is grounded via diode D, resistor R3,
A connection between the diode D and the resistor R3 (the voltage here is V3) is connected to the "1" terminal of the comparator 7. The output terminal of comparator 7 is connected to the bases of NPN transistors Q5 and Q6, the collector of this transistor is connected to the collector of transistor Q, the collector of transistor Q6 is connected to output terminal 12, and the transistor is connected to the emitter of Q6. is grounded. FIG. 2a shows a specific example of the attenuator section 2 in FIG. 1, where the voltage V4 at one end of the resistor R is expressed as V4=
Vref.

即ち差動入力段トランジスタQ・2,Q,3のェミッタ
電圧は同一であり、トランジスタQ,.のベースには、
抵抗R,.,R,2による分割電位に対応する基準電圧
Vrefが与えられているから、通常状態では、トラン
ジスタQ・4のべ−ス電圧V4=Vrefである。ここ
でV4が上昇しようとすると、トランジスタQ,4,Q
,3がオフとなり、Q,.,Q,2がよりオン状態とな
る。従ってトランジスタQ,6,Q,5がオフとなり、
これによりトランジスタQ,7がオフ、Q,8,Q,が
オンとなり、V4を下げる。一方、V4が基準VrMよ
り下ろうとすると、トランジスタQ,4,Q,3がより
オン状態となり、トランジスタQ・・,Q・2はオフと
なる。これによりトランジスタQ,6,Q,5がオンと
なり、Q,7がオン、Q,3,Q,がオフとなり、V4
が上昇する。従って常にV4=Vrefであり、入力V
inが供V給された時抵抗R,,Rx間のV4レベルは
、Vrdの値と抵抗Rx,R,の抵抗比より決まり、V
.!V喪章−十V青;XR.十V花r ……【
11となる。この時のアッテネータ部2の等価回路は第
2図bに示される。次に第1図の回路動作を説明する。
That is, the emitter voltages of the differential input stage transistors Q2, Q, and 3 are the same, and the emitter voltages of the transistors Q, . At the base of
Resistance R,. , R, 2, the base voltage V4 of the transistor Q4 is Vref in the normal state. Here, if V4 tries to rise, transistors Q, 4, Q
, 3 are turned off, and Q, . , Q,2 become more on-state. Therefore, transistors Q, 6, Q, 5 are turned off,
As a result, transistors Q, 7 are turned off, transistors Q, 8, and Q are turned on, and V4 is lowered. On the other hand, when V4 attempts to fall below the reference VrM, transistors Q, 4, Q, 3 become more on, and transistors Q.., Q.2 become off. As a result, transistors Q, 6, Q, 5 are turned on, Q, 7 is turned on, Q, 3, Q, are turned off, and V4
rises. Therefore, V4=Vref always, and the input V
When in is supplied with V, the V4 level between the resistors R, and Rx is determined by the value of Vrd and the resistance ratio of the resistors Rx, R, and V
.. ! V mourning band - 10 V blue; XR. 10V Hana r...[
It becomes 11. The equivalent circuit of the attenuator section 2 at this time is shown in FIG. 2b. Next, the operation of the circuit shown in FIG. 1 will be explained.

まず一例として下記の如き条件を定め、入力V:nが変
化した時のオベアンプ6の入力電圧V,、出力スレッシ
ョルド電圧Vth(コンパレータの反転電圧)を求めて
みる。Vrefニ0.1V、Rx=1級Q、R,=秋○
、R2=10kQ、R3:5kQ、1,!20仏A、1
2ニ15仏A ・■ Vin=0.2Vの時:V.=会
う芸;XR.十V似=¥三等X3十0.1≠0.114
〔V〕≠V2ここでV,とV2が等しくなるのはオベア
ンプ6の作用による。
First, as an example, the following conditions are set, and the input voltage V of the oven amplifier 6 and the output threshold voltage Vth (inversion voltage of the comparator) when the input V:n changes are determined. Vref Ni 0.1V, Rx = 1st class Q, R, = Autumn○
, R2=10kQ, R3:5kQ, 1,! 20 Buddha A, 1
2 Ni 15 Buddha A ・■ When Vin=0.2V: V. =The art of meeting; XR. 10V similar = ¥3rd class x 300.1≠0.114
[V]≠V2 The reason why V and V2 become equal here is due to the action of the oven amplifier 6.

上記計算結果から、抵抗R,に流れる電流はV2/R2
=11.4〔仏A〕となり、この値は定電流1川こよる
電流a,=20仏A以下であるから、この状態ではカレ
ントミラー8は動作しない。従って抵抗R3を流れる電
流は定電流源1 1による電流12のみであり、電圧V
3はV3=12×R3=75〔mV〕
・・・・・・‘2)で決まり、この場合出力スレツシ
ョルド電圧Vthは75mVとなる。
From the above calculation results, the current flowing through the resistor R is V2/R2
=11.4 [A], and this value is less than the current a caused by one constant current, =20 A, so the current mirror 8 does not operate in this state. Therefore, the current flowing through the resistor R3 is only the current 12 from the constant current source 11, and the voltage V
3 is V3 = 12 x R3 = 75 [mV]
...'2), and in this case, the output threshold voltage Vth is 75 mV.

つまり電圧V,が、1.×R2=0.2〔V〕の値を越
えるまで電位V2は0.2〔V〕となりV比は{2}式
で決まるものである。ここで電圧V,が1,×R2の値
を越え、カレントミラー回路8が動作し始める時のVi
nの値を求めると、m式よりV;n=位x+R,)W,
一Vref)+VrefiR,Q8十3)(芸‐2−。
That is, the voltage V, is 1. The potential V2 becomes 0.2 [V] until it exceeds the value of ×R2=0.2 [V], and the V ratio is determined by the formula {2}. Here, the voltage V, exceeds the value of 1,×R2, and the current mirror circuit 8 starts operating.
When calculating the value of n, from the m formula, V; n = position x + R, ) W,
1 Vref) + VrefiR, Q8 13) (Art-2-.

‐1)十。‐・:。‐8〔V〕となる。■ Vin=5
Vの時: V.=と声¥X3十0‐1=0‐8〔V〕この時V2=
0.8〔V〕になろうとし、コンデンサC,にはV2=
0.8〔V〕とする電圧が蓄積され、その時抵抗R2に
流れる電流IR2はV2− 0.8 IR2=R2一応万両=80〔〃A〕 1,=20仏Aが抵抗R2に流れているため、この差6
0仏Aがカレントミラー回路8からR2に供給される。
-1) Ten. -・:. -8 [V]. ■ Vin=5
When V: V. = voice ¥X300-1=0-8 [V] At this time V2=
0.8 [V], and capacitor C has V2=
A voltage of 0.8 [V] is accumulated, and at that time, the current IR2 flowing through the resistor R2 is V2 - 0.8 IR2 = R2 10,000 ryo = 80 [A] 1, = 20 A flows through the resistor R2. Therefore, this difference is 6
0 French A is supplied from the current mirror circuit 8 to R2.

カレントミラー8ではトランジスタQ3のコレクタ側電
流(=60仏A)と等しい電流が抵抗R3に流れ、その
電流をIR3とすればIR3=60十12ニ75〔ムA
〕 V3こIR3×R3=75×6=0.375〔V〕この
時の出力スレッショルド電圧Vthは、V,=0.37
5〔V〕を越えた時の値であるから、V山=(R,十R
XXV,−Vref)Vref=7×〇.275十〇.
・ニR,2.03〔V〕 これは次のVinのサイン半波電圧に対するスレツショ
ルド電圧となり、つまり一つおくれのサイン波Vin=
2.03〔V〕となっている間、出力トランジスタQ,
の出力端子12が接地レベルとなるものである。
In the current mirror 8, a current equal to the collector side current of the transistor Q3 (=60 mm A) flows through the resistor R3, and if that current is IR3, then IR3 = 60 112 75 mm A
] V3 IR3 x R3 = 75 x 6 = 0.375 [V] The output threshold voltage Vth at this time is V, = 0.37
Since this is the value when exceeding 5 [V], V mountain = (R, 10R
XXV, -Vref) Vref=7×〇. 275 hundred.
・R, 2.03 [V] This is the threshold voltage for the next sine half wave voltage of Vin, that is, the next sine wave Vin=
While the voltage is 2.03 [V], the output transistor Q,
The output terminal 12 of is at ground level.

■ Vin=50〔V〕の時: V.=聖裏!X3十o‐1=7‐23〔V〕前記■項の
場合と同様にして・舷=毒等を=o‐723〔mA〕 また0.723一1,=0.703〔mA〕だからIR
3=0.703十12=0.718〔mA〕/.V3=
3.59〔V〕.・.Vth=7×(3.59−0.1
)十0.1〒24.5〔V〕となる。
■ When Vin=50 [V]: V. = Holy back! X30 o-1 = 7-23 [V] In the same way as in the case of section ■ above, the ship = poison, etc. = o-723 [mA] Also, 0.723 - 1, = 0.703 [mA] Therefore, IR
3 = 0.703 + 12 = 0.718 [mA]/. V3=
3.59 [V].・.. Vth=7×(3.59-0.1
) 10.1〒24.5 [V].

第3図は以上の計算例に従がうV;n−Vth特性図で
ある。
FIG. 3 is a V;n-Vth characteristic diagram according to the above calculation example.

即ち第1図の回路は、V,の値が電流1.及び抵抗R2
による設定値を越えない場合に、電流12及び抵抗R3
の設定値により電圧検出を行ない、入力Vinのレベル
が大となってV,の値が1,,R2いよる設定値を越え
てからは、略R3/R2の値で検出電するものである。
上記の如き電圧検出回路には、次のような利点が具備さ
れる。
That is, in the circuit of FIG. 1, the value of V is 1. and resistance R2
current 12 and resistance R3 if the set value is not exceeded by
Voltage detection is performed according to the set value of , and after the level of input Vin becomes large and the value of V exceeds the set value of 1, R2, the voltage is detected at approximately the value of R3/R2. .
The voltage detection circuit as described above has the following advantages.

即ち入力Vinに応じてスレツショルド電圧Vthが変
化するので、入力Vinのノイズに影響されず、広範囲
に変動する入力電圧を精度よく検出できる。またオベァ
ンプ入力電圧V.の値は、基準電圧Vrefと抵抗Rx
,R,の分圧比を変えることにより任意の値に圧縮でき
るので、電源Vccより高い電圧を入力Vinに用いて
検出することもできる。またオベアンプ4及びトランジ
スタQ,で基準電圧V4(=Vr封)を得るようにして
いるので、抵抗Rx,R,の電流値により基準電圧誤差
つまり電圧検出誤差が生じない。なお本発明は上記実施
例のみに限定されるものではなく、例えば入力Vinを
圧縮しなくてもよい場合にはアッテネータ部2を省略し
てもよいし、また用途によっては定電流源10,11と
が、トランジスタQ5,Qを省略してもよい等、種々の
応用が可能である。
That is, since the threshold voltage Vth changes according to the input Vin, it is not affected by the noise of the input Vin, and it is possible to accurately detect an input voltage that fluctuates over a wide range. Also, the amplifier input voltage V. The value of is the reference voltage Vref and the resistance Rx
, R, can be compressed to an arbitrary value by changing the voltage division ratio, so a voltage higher than the power supply Vcc can be used for the input Vin for detection. Further, since the reference voltage V4 (=Vr sealed) is obtained by the oven amplifier 4 and the transistor Q, a reference voltage error, that is, a voltage detection error does not occur due to the current values of the resistors Rx and R. Note that the present invention is not limited to the above-mentioned embodiments. For example, if the input Vin does not need to be compressed, the attenuator section 2 may be omitted, and depending on the application, the constant current sources 10 and 11 may be omitted. However, various applications are possible, such as the transistors Q5 and Q may be omitted.

以上説明した如く本発明によれば、被検出入力電圧のレ
ベルに応じて出力スレッショルド電圧を変化できるので
、広範囲の変化をする入力電圧の検出が精度よく行なえ
る電圧検出回路が提供できるものである。
As explained above, according to the present invention, since the output threshold voltage can be changed according to the level of the input voltage to be detected, it is possible to provide a voltage detection circuit that can accurately detect input voltages that change over a wide range. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路図、第2図aは同
回路の一部詳細回路図、第2図bはその等価回路図、第
3図は第1図の回路のVin一Vth特性図である。 1・・・・・・入力端子、2・・・・・・アツテネータ
部、4・・・5・・・オベアンプ、6…・・・オベアン
プ、7・・・・・・コンパレータ、8……カレントミラ
ー回路、10,11・・・・・・定電流源、Rx,R,
〜R3・・・・・・抵抗、Q,〜Q6・・・…トランジ
スタ、C,”””コンテーンサ。 第1図第2図 第3図
Figure 1 is a circuit diagram showing an embodiment of the present invention, Figure 2a is a partial detailed circuit diagram of the same circuit, Figure 2b is its equivalent circuit diagram, and Figure 3 is a Vin diagram of the circuit in Figure 1. 1 is a Vth characteristic diagram. 1...Input terminal, 2...Attenuator section, 4...5...Obe amplifier, 6...Obe amplifier, 7...Comparator, 8...Current Mirror circuit, 10, 11...constant current source, Rx, R,
~R3... Resistor, Q, ~Q6... Transistor, C, """ Capacitor. Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】 1 入力電圧に応じた電圧を供給する電圧供給部と、こ
の電圧供給部からの電圧を入力とするオペアンプと、こ
のオペアンプの出力に応じた電流を第1の通電路に流し
この通電路の電流に応じた電流を第2の通電路に流すカ
レントミラー回路と、前記入力電圧のピーク値に応じた
電圧を記憶しこの電圧に応じた前記第1及び第2の通電
路の電流を保持するための電圧記憶手段と、前記第2の
通電路の電流値に応じた電圧と前記電圧供給部により与
えられる電圧とを比較する比較手段とる具備したことを
特徴とする電圧検出回路。 2 電圧供給部が複数の抵抗と定電圧源とを直列接続し
たアツテネータであることを特徴とする特許請求の範囲
1に記載の電圧検出回路。 3 入力電圧に応じた電圧を供給する電圧供給部と、こ
の電圧供給部からの電圧を入力とするオペアンプと、こ
のオペアンプの出力に応じた電流を第1の通電路に流し
この通電路の電流に応じた電流を第2の通電路に流すカ
レントミラー回路と、前記入力電圧のピーク値に応じた
電圧を記憶しこの電圧に応じた前記第1及び第2の通電
路の電流を保持するために用いる電圧記憶手段と、前記
第1の通電路の電流に定電流を加えた第1の電流を流す
第1の定電流源と、前記第2の通電路の電流に定電流を
加えた第2の電流を流す第2の定電流源と、前記第2の
電流の値に応じた電圧と前記電圧供給部により与えられ
る電圧とを比較する比較手段とを具備したことを特徴と
する電圧検出回路。 4 電圧供給部が複数の抵抗と定電圧源とを直列接続し
たアツテネータであることを特徴とする特許請求の範囲
3に記載の電圧検出回路。
[Claims] 1. A voltage supply unit that supplies a voltage according to an input voltage, an operational amplifier that inputs the voltage from this voltage supply unit, and a current that corresponds to the output of this operational amplifier to a first current-carrying path. a current mirror circuit that causes a current corresponding to the current in this current-carrying path to flow through a second current-carrying path; and a current mirror circuit that stores a voltage corresponding to a peak value of the input voltage, and stores the voltage corresponding to the peak value of the input voltage, and the first and second current-carrying paths that correspond to this voltage. voltage storage means for holding the current of the current, and comparison means for comparing the voltage according to the current value of the second current-carrying path and the voltage given by the voltage supply unit. circuit. 2. The voltage detection circuit according to claim 1, wherein the voltage supply section is an attenuator in which a plurality of resistors and a constant voltage source are connected in series. 3. A voltage supply section that supplies a voltage according to the input voltage, an operational amplifier that receives the voltage from this voltage supply section, and a current that corresponds to the output of this operational amplifier is passed through a first current-carrying path to generate a current in this current-carrying path. a current mirror circuit that causes a current to flow in the second current path according to the input voltage; a first constant current source that supplies a first current obtained by adding a constant current to the current in the first current carrying path; Voltage detection characterized by comprising: a second constant current source that flows a current of No. 2; and comparison means that compares a voltage according to the value of the second current and a voltage provided by the voltage supply unit. circuit. 4. The voltage detection circuit according to claim 3, wherein the voltage supply section is an attenuator in which a plurality of resistors and a constant voltage source are connected in series.
JP16320278A 1978-12-27 1978-12-27 voltage detection circuit Expired JPS6031267B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16320278A JPS6031267B2 (en) 1978-12-27 1978-12-27 voltage detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16320278A JPS6031267B2 (en) 1978-12-27 1978-12-27 voltage detection circuit

Publications (2)

Publication Number Publication Date
JPS5587957A JPS5587957A (en) 1980-07-03
JPS6031267B2 true JPS6031267B2 (en) 1985-07-20

Family

ID=15769212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16320278A Expired JPS6031267B2 (en) 1978-12-27 1978-12-27 voltage detection circuit

Country Status (1)

Country Link
JP (1) JPS6031267B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0230495U (en) * 1988-08-12 1990-02-27
JPH03129048U (en) * 1990-04-12 1991-12-25

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0230495U (en) * 1988-08-12 1990-02-27
JPH03129048U (en) * 1990-04-12 1991-12-25

Also Published As

Publication number Publication date
JPS5587957A (en) 1980-07-03

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