JPS6030879Y2 - Pre-waveform storage - Google Patents

Description

[Detailed Description of the Invention] The present invention is intended to provide a waveform storage device that can be added to an existing waveform storage device such as a MOS LSI to easily increase its writing speed.

Currently, the main type of waveform storage devices that are used extensively in various fields of science and engineering are digital systems.

These are excellent devices that have several features not found in storage oscilloscopes, which are conventional devices for the same purpose, but their writing speed depends on the clock frequency of the storage circuit and the
It is strongly limited by the conversion speed of the /D converter and cannot necessarily be said to be sophisticated.

In particular, in models whose memory circuits are constructed from MOS-type integrated circuits, the degree of integration of the memory IC is high, which allows for miniaturization and low equipment costs. The allowable upper limit frequency of the input signal is also on the order of several tens of KH2.

For faster models, A/D, D/A converters,
Memory circuits are also extremely complex, large-scale, and usually extremely expensive.

The present invention is intended to simply and effectively increase the writing speed (storage speed) of the above-mentioned inexpensive but slow waveform storage device by adding it to the front.

As mentioned above, A/D and D/A conversion circuits are one of the circuits that become large-scale when speeding up.

In order to increase the storage speed of a digital waveform storage device, the speed of the memory itself must be increased, as well as the speed of the A/D and D/A converters placed before and after the memory element.

Normally, increasing the speed of this part necessarily accompanies the complexity of the circuit.

In contrast, the device of the present invention uses an analog memory element such as a CCD, as shown in Fig.
/D, D/A conversion is essentially omitted.

That is, since the input signal is stored as an analog quantity, an A/D converter for processing high-speed signals is not required.

In this way, by employing an analog memory element in the memory circuit, the entire device is greatly simplified, and the upper limit frequency that can be used by the main device can be expanded at low cost.

This device writes an input signal into an analog storage element such as a CCD using a high-speed clock pulse corresponding to a high-speed input signal, and then stores the contents of the storage element using a clock pulse synchronized with the clock pulse of a subsequent low-speed main waveform storage device. It uses pulses to read and write to the main device with high retention characteristics at the same time.

At present, it is already known that the frequency of the possible lock pulse reaches about m times that of the MO3LSI memory in CODs used for video signal delay and the like.

However, on the other hand, the long-term preservation of the signals of these analog storage elements is due to the fact that the principle of storage is analog charge accumulation in capacitance, which preserves the stable state of the circuit.
Digital MOS LIS that targets only values
It is significantly inferior compared to memory and the like.

The key point of the present invention is to simply realize a high-speed waveform storage device as a whole by combining the advantages and disadvantages of both analog and digital methods.

Now, in FIG. 1, 1 is an input terminal, and the signal to be processed is adjusted to an appropriate scale from 1 to a storage element such as a CCD via an attenuator 2 and an amplifier 3.

The data then passes through a high-speed analog switch 4 and enters a storage circuit 5 consisting of a CCD and the like.

The drive pulses required for memory circuit 5 are generated by drive circuit 7.

The clock pulse input to this drive circuit 7 is switched between the W mode and the R mode by a switch 8.

Specifically, W is a write state, and R is a read state.

At position W, a high speed clock pulse is applied to 7 so that the storage circuit 5 also quickly receives the input signal.

At position R, a pulse generated by a low-speed clock pulse generation circuit synchronized with a clock pulse of a main waveform storage device such as a subsequent digital system or the clock pulse itself used by the main waveform storage device is added to 7.

9 is a high-speed clock pulse generation circuit for writing.

In principle, this circuit does not need to be particularly connected to the subsequent main device, but if the clock pulse of the subsequent device is to be used as a time reference in the preceding device, the main device's clock They may be combined by pulse circuits, PLLs, or other methods such that a particular frequency relationship exists between both clock pulses.

However, in general, its independence is higher than that of a clock pulse circuit for reading.

Reference numeral 11 denotes a low-speed clock pulse generation circuit for reading, which generates pulses in synchronization with clock pulses during writing of the subsequent main waveform storage device.

This circuit may be omitted when clock pulses are obtained and used directly from a subsequent waveform store.

Reference numeral 10 counts clock pulses to measure the usage of cells of elements such as CCDs in the memory circuit, and controls analog switches 4 and 6 and switches 8.

Note that this switch 8 is in charge of passing control and switching of the clock pulse, and functions as a digital gate.

The operation of each of these 4°6.8 switches well indicates and characterizes the operation of the present device.

First, when writing input signals, analog switch 4
is in the on state, and another analog switch 6
is in the off state, and switch 8 is in the W position.

In this way, the input signal and writing clock pulse are
A state is created in which the input signal is applied to the memory circuit 5, and as described above, the input signal is stored in the memory circuit 5 by high-speed clock pulses.

After this, writing continues and when all cells of the memory element are filled, the control circuit of each of the 10 switches counting clock pulses issues an output signal to turn off the analog switch 4.
is turned on, and at the same time, the switch 8 is set to the R position.

As a result, the signal stored in 5 is read out in accordance with the writing in the subsequent waveform storage device and transferred to the subsequent device.

The completion of reading is monitored by 10 circuits in the same manner as during writing, and each switch returns to its initial state after counting for all cells of the storage element is completed.

Afterwards, this write and read cycle is repeated, but if it is inconvenient to repeat it, for example, an R-S flip-flop is provided in the control circuit 10 so that it can be returned to the initial state by manual reset etc. It is also possible to do so.

The improvement in performance due to the addition of this device is that, as mentioned above, the upper limit of the clock frequency of CCDs, etc. is more than double that of the clock pulse of MOS LSI memory, but due to the low signal storage properties of CCDs, etc., it is difficult to read out data too slowly. Therefore, the frequency ratio of write and read clock pulses is not necessarily doubled, and the improvement rate of storage speed remains below 0 times.
It is possible to increase the storage speed of a waveform storage device using an LSI several times or more.

The circuits required for this purpose include an analog memory circuit and a high-speed analog switch, which belong to a somewhat special category, but others are general digital circuits, etc., and it is especially necessary to add and install this device. We won't ask you to spend a lot of money.

Considering the above-mentioned items and looking at the overall performance, based on this principle, a semi-analog waveform storage device using this device is much cheaper than a pure digital waveform storage device with the same performance. .

Note that the above-mentioned performance is based on the current level of devices, and it goes without saying that the storage speed can be further improved if faster, higher retention storage devices are developed.

The method of the present invention that uses analog temporary storage is essentially suitable for high-speed waveform storage because it does not require high-speed A/D conversion.

While increasing the speed of a digital waveform storage device requires an extremely large scale, this method is a powerful method for providing a high-speed waveform storage device at a low cost.

This device can be used immediately as a waveform storage device as a measuring instrument, but since this device has enough accuracy to withstand use as a measuring instrument, it can also be used for storage purposes other than measurement. It is.

Although the memory circuit 5 using a CCD or the like in FIG. 1 may seem like a special circuit in this device, it is actually a delay circuit that is very basic in the application of CCDs and is generally well known. The circuit shown can be applied as is.

That is, after applying an appropriate power supply voltage to an element such as a CCD, a clock pulse is sent to a designated pin, and an input signal is applied to another designated pin.

In addition, there are several known modified circuits of this delay circuit with various improvements, each of which has excellent functions, and these can also be used to their fullest potential.

For example, a circuit that uses two BBDs to effectively obtain a sampling rate twice the frequency of the clock pulse is known as a useful circuit, but this can also be used as is in the circuit 5. Its value is especially great because it is aimed at

A method similar to this is sometimes used in digital storage circuits, but digital waveform storage devices have problems with A/D converters as mentioned above, so it is not possible to simply make the storage circuit faster. The overall storage speed of the device does not improve.

However, this method is very effective in the present frontal device.

That is, according to this method, the storage speed of a BBD or the like can be easily doubled, and this can also immediately double the storage speed of the device.

Since the clock pulse frequency of the current medium-speed BBD is already almost the same as that of MOS LSI memory, if the storage speed to the BBD is doubled in this way, this device will be able to increase the speed of MOS LSI memory. Doubling the storage speed of a waveform storage device using a memory element is possible with a BD, which is easily available for general use.

The fact that the device of the present invention requires only one or two high-speed memory elements as described above is a major advantage compared to digital devices that normally require at least eight or more high-speed memory elements. be.

Each of the other blocks also has standard circuitry.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle and structure of the pre-waveform storage device of the present invention. In the figure, each block represents a functional circuit part,
The solid line shows the flow path of the signal and clock pulse, and the broken line shows the action light of the control signal. Furthermore, the area within the dashed-dotted line represents the waveform storage device of this device, and the subsequent waveform storage device is shown outside the dashed-dotted line.

Claims (1)

[Scope of utility model registration request] Charge Coupled Device, B
A high-speed analog delay element (hereinafter referred to as CCD, etc.) such as a Ucket Brigade Device is used as a temporary storage circuit, and a clock pulse circuit for high-speed writing provided for this storage circuit and reading synchronized with subsequent writing to the waveform storage device are used. A waveform memory device that is installed in front of a waveform memory device such as a digital type, and has an introduction path for clock pulses from a clock pulse circuit or a subsequent waveform memory device, and has a switch for switching the clock pulses when writing and reading input signals. Device.