JPH0555503A - Memory device - Google Patents

Abstract

PURPOSE:To provide a memory device which employs one electron as a unit of storage. CONSTITUTION:A title device composed of fine junction area tunneling capacitors J1 and J2 (whose capacitances are C1 and C2, respectively) and a resistor R is known to operate as a triode amplifier (transistor) in an one electron unit on the conditions of e<2>/C1, e<2>/C2>>kBT (e: electron charge, kB: Boltzmann's constant, T: absolute temperature). The transistor and a capacitor are interconnected with each other. Charging and discharging on and from the capacitor C are controlled by controlling biasses U and V in a good timing, and also electric charges on the capacitor are kept at their held state. Thus, a high density memory is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device including a three-terminal amplifier using a minute tunnel element and a capacitor.

[0002]

2. Description of the Related Art Although a storage element having one electron as a unit of storage is the smallest possible memory, it may be described as a concept, but a specific configuration and operation will be described. There was nothing I did. If a storage device with one electron as a unit can be realized, an extremely small storage operation with extremely low power consumption can be realized.

[0003]

According to the present invention, two tunnel junctions having a minute area and a minute capacitance are connected in series, and one end of a resistance element is connected to the connection point to form a three-terminal element. None, one end of the capacitor is connected to one tunnel junction, the other end of this capacitor is grounded, the other end of the tunnel junction opposite to the capacitor is used as a read / write electrode, and the other end of the resistance element is controlled. It is a storage device characterized by using an electrode. The resistance element may be replaced with a capacitor.

[0004]

FIG. 1 is a circuit diagram (a) showing an embodiment of the present invention and a diagram (b) showing the operating principle.

In FIG. 1A, tunnel capacitors J ₁ and J _{2 having} extremely small areas (capacitances thereof are C ₁ and C ₂ respectively) and a resistance R are Rikarev (KK).
Is a three-terminal one-electron transistor proposed by (IE ³ Trans. ^On Mag. VolMAG-2.
3, No. 2, March, 1987, p1142-1.
145). Let the three terminals be T ₁ , T ₂ and T ₃ , respectively.
This element is ^{_{e 2 / C 1, e 2}} / C 2 >> k B T (e: electron charge, k _B: Boltzmann constant, T: absolute temperature) as a three-terminal amplifier in one electronic unit when the (transistor) Operate. A capacitor C is connected to the terminal T _2, and the other terminal of the capacitor is grounded.

The operation of the transistor will be described with reference to FIG. However, the charge Q _{s of the} capacitor is set to 0. Terminal T
_When bias U is applied to ₃ and bias V is applied to terminal T ₁ , the number of electrons passing through tunnel capacitor J ₁ in the direction of the arrow is n ₁ , and the number of electrons passing through tunnel capacitor J ₂ in the same direction is n. _Set to ₂ . At this time, the free energy F of the system is shown below.

[0007]

[Equation 1]

From the above equation, the following equation is obtained.

[0009]

[Equation 2]

The region of equations (9) and (10) is shown in the UV plane in the quadrangle of FIG. 1 (b). The quadrilateral of FIG. 1B has U = ± 1/2 · e / Cε and V = U ± e / 2Cε as quadrilaterals. However, when Cε = C ₁ + C ₂ , C ₁ and C ₂ are the capacities of the tunnel junctions J ₁ and J ₂ , respectively, and e is the electron charge (e> 0). Inside this quadrilateral (n ₁ , n
₂ ) (however, n ₁ = n ₂ ) is maintained and no current flows through the transistor. The internal I of this quadrilateral is (n ₁ , n
₂₎ state and in the transverse the upper and lower sides when n ₁ is ± 1 changes of, n ₂ varies ± 1 crosses the left and right two sides. In the figure, the values of n ₁ and n ₂ in the area divided by the four sides and their extension lines are shown. For example region II or U
> E / 2Cε, V> U + e / 2Cε (n ₁ +1, n
₂ +1), one electron passes through J ₁ and J ₂ ,
A current of electric charge e flows. Here, the capacitor C is given by the following equation by the insulating film thickness d, the electrode area S, and the dielectric constant E of the insulating film.

C = S / Ed (11) As specific numerical values, d = 1 nm, S = (10 nm) ² ,
When the relative dielectric constant _{E r = 8 C = 5.5 ×} 10 - a ^{1 8} F. Further, since a tunnel current flows through the capacitor, it is represented by a tunnel resistance at a low voltage, but this value is about 5 × 10 ^{6 to} 9 × 10 ⁸ Ω. C = 5x
The scale of voltage V and temperature T when 10 ⁻¹⁸ F is shown below.

[0012] V = e / C = 1.6 × 10 - 1 9/5 × 10 - 1 8 = 0.03V = 30mV T << eV / k B = 30 × 10 - 3 /8.617×10 - ⁵ = 350K Since these values do not always represent the current values,
When indicating the normal value in the ^{current, C = 5 × 10 - 1} 5 F
As a result, V = 30 μV, T << 0.35K In FIG. 2, a diagram of a quadrangle when the charge Q = 0 and Q = e of the capacitor is overlaid. Here, the capacitance C of the capacitor C
_{Let S} = 2Cε. Therefore, the bias between the capacitors when Q = e is V _s = Q / C _S = e / 2Cε. Therefore, the quadrangle when Q = e is translated by V _{S in the} U direction and the V direction. The operation of the memory will be described below with reference to these figures.

Holding state : This is the state of the operating point S in FIG. At this time, the charge Q is held in the capacitor C in the state of Q = 0 or Q = e.

Read cycle : The operating point moves from S to R along the dotted line as shown in the figure. When Q = 0, it goes out of the quadrangle of Q = 0 and changes like n ₁ → n ₁ +1 and n ₂ → n ₂ +1 and the current corresponding to one electron is J ₁ , J ₂ This current is detected in the external line. At this time, the charge of the capacitor changes to Q = e.

On the other hand, when Q = e, since R is inside the quadrangle of Q = e, no external current is detected. (U, V)
After reading the data of the memory cell by operating S → R, the data of the cell is “1” regardless of the initial data. Next, even if (U, V) is returned from R to S, this state is maintained because the movement is inside the quadrangle in the "1" state. Since this read is destructive read, it must be written back, which will be described later.

If a “1” write cycle (U, V) is operated as S → R → S as in the read cycle, 0 → 1,
Writing is performed as 1 → 1.

“0” write cycle (U, V) is S
→ W → S "0" is written by S → W regardless of the contents of the cell. Since the movement from W to S is within the "0" quadrilateral, the state of "0" is held and the "0" write cycle is completed.

The above is summarized in Table 1 below.

[0019]

[Table 1]

Read circuit (sense circuit and write back (restore) circuit). FIG. 3 shows a sense circuit for reading. In the read cycle, it is not possible to control the distinction between the read operation and the "1" write operation only by moving (U, V), so the sense circuit performs this. The read operation is destructive read, but the sense circuit is used to perform a restore operation to write it back in the read cycle.

[0021] The closed switch S _W in FIG. 3 when the light,
S _{R 1} opens and the cell connects to a write circuit (not shown). The write circuit may be any circuit that outputs a pulse of voltage V, and no special device is required. Switch S _W is opened in read operation, the cell closes S _R is coupled with read circuit. To read, S _V and S with S _{R 2} open
_R1 is closed, and (U, V) of the memory cell is S in FIG. 3 (b).
→ Move to S '. It is assumed that S'is in the "0" state and is very close to the "1" state. Then S
_{R 1} is opened and the potential of the capacitor C _D is set to V ′. C _D is a very small capacitance, and tunnel capacitors C ₁ and C
_Suppose it is less than ₂ . However, it is assumed that the insulating film forming this capacitor is sufficiently thick so that no tunnel current flows. After this capacitor is charged to the potential V ′ and the switch S _V is opened and S _{R 1} is closed, the potentials of the capacitor C _D and the cell electrode T ₁ become the same, and the capacitor moves to R ′ in FIG. 3B. .. At this time, it is determined whether or not electrons are emitted from the cell depending on whether the holding state of the memory cell is "0" or "1". The current caused by the electrons is detected by the potential change of the capacitor C _D. At this time, the output signal from the cell is amplified by the high-sensitivity amplifier 30 having the threshold value set to the intermediate value of the respective potentials V at the points R'corresponding to the "0" and "1" levels. .. Then switch S _{R 1} ,
Open S _{R 2} . The output of the amplifier 30 is stored in a normal latch circuit such as a flip-flop circuit. Restore size
The reading is completed when the clock is over. Next, in order to perform restoration, the switch S _R is opened, S _W is closed, and the write operation is started. Restoration is completed by writing to the cell in accordance with the read latched signal.

FIG. 4 shows a second embodiment of the present invention. In this example, as shown in FIG. 7A, a capacitor C ₃ is used instead of using the resistance element R for the signal input terminal of the transistor in the first embodiment. All other configurations are similar to those of the first embodiment. FIG. 4B shows an operating region of the transistor. In the figure, Cε = C ₁ + C ₂ + C ₃ . Like the inside of the quadrilateral shown in solid lines in FIG When (n _1, n ₂₎ in area and FIG. 1 (b), n ₁ → n ₁ +1 crosses the left upstream side, downhill N ₁ → n ₁ −1 when crossing the side in the direction of, and n ₂ when crossing the side in the upper right direction
→ n ₂ +1 and n ₂ → n ₂ −
Change to 1.

FIG. 5 is a state area diagram showing the operation of the memory. The figures of the quadrangle when the charge Q = 0 and Q = e of the capacitor are overlaid. Here, the capacitance C _S of the capacitor C
Is selected so that the lower left corner point of the quadrangle when Q = e comes to the center of gravity of the quadrangle at Q = 0. If the meanings of the operating points of R and W are the same as in the first embodiment, basically the same operation, write circuit and sense circuit can be used, and the operation is also the same.
The merit of this circuit is that a fast pulse response is possible because the input to the one-electron transistor is the capacitance C ₃ .

FIG. 6 shows an example in which the contact N of the one-electron transistor of this circuit is provided with a switch 60 for resetting. Thereby, the initial charge Q ₀ of the contact N can be set to 0. Since Q ₀ = 0 was assumed in the embodiment of FIG. 3, this reset switch 60 is actually required.

FIG. 7 shows an example in which a switch 70 for resetting the initial value of the charge stored in the capacitor of the memory cell is provided in parallel with the cell capacitor C ₇ . As a result, the initial value of the cell capacitor can be quickly adjusted to the "0" value.

[0026]

According to the present invention, a memory having one electron as a storage medium can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory showing a first embodiment of the present invention and a diagram for explaining the operation thereof.

FIG. 2 is a diagram illustrating the operation of the memory of the present invention.

FIG. 3 is a diagram showing a sense circuit.

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a state region diagram showing the operation of the memory.

FIG. 6 is a diagram showing an example including a reset switch.

FIG. 7 is a diagram showing an example in which a reset switch for resetting an initial value of an electric charge stored in a capacitor of a memory cell is provided.

[Explanation of symbols]

J ₁ , J ₂ tunnel capacitor R resistance C, C ₃ , C ₇ capacitors T ₁ , T ₂ , T ₃ terminal 30 amplifier 60, 70 reset switch

Claims (2)

[Claims] 1. A tunnel junction having a small area and a capacitance is connected in series, one end of a resistance element is connected to the connection point to form a three-end element, and one end of a capacitor is connected to one tunnel junction. Then, the other end of the capacitor is grounded, a terminal of the other tunnel junction opposite to the capacitor is used as a read / write electrode, and the other end of the resistance element is used as a control electrode. 2. The resistance element is changed to a capacitor.
Storage device according to.