JPS6029843A - Microprogram controller - Google Patents

Abstract

PURPOSE:To reduce the probability of error occurrence to a control memory in a stage of actual instruction execution and to improve the reliability by reading a control word out of the control memory and making a diagnosis at specific intervals of time, and correcting an error if the error occurs and rewriting the control words. CONSTITUTION:A diagnostic instruction is generated at constant intervals of time to access the control memory 1, and when a flag 31 indicating the read control word is a specific control word is detected, a control circuit 7 is actuated for diagnosis. If an error is detected here, an error correcting code logical mechanism corrects this control word, sets the corrected data in a write register 4, and rewrites it in the control memory 1. This operation is repeated at constant intervals of time to read and check all control words eventually, and an error is corrected once occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION fal Technical Field of the Invention The present invention relates to a method for diagnosing control words in a microprogram-controlled data processing device.

(bl Background of the Technology) When a microprogram-controlled data processing device has an error correction code logic mechanism for control words, it is common to use a control word modified by the error correction code logic mechanism described above. In the case where the next microaddress is determined by itself, there is a problem in that it is not possible to convert the /iii arithmetic cycle related to the control storage unit due to the logical delay required for error correction.

One solution to this problem is to execute maintenance commands at fixed time intervals in the sense of preventive maintenance, and if an error occurs, the control word is corrected at that point, so that the error can be avoided during the actual execution of the command. Since it can reduce the probability of detection, its implementation has been desired.

(C1 Prior Art and Problems A control word corrected by error correction code logic (hereinafter referred to as ECC) is written into the control storage unit. In data processing devices, control words are normally checked by ECC, but A control word that has not been corrected by ECC is used for the arithmetic unit, and if a 1-bit error occurs, the instruction is interrupted, the control word where the error occurred is rewritten, and the instruction is retried again. I had adopted a method of doing so.

However, with this method, not all commands can be retried, which poses a problem that seriously affects the system.

(d) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention, in the sense of preventive maintenance, reads the control word from the control storage unit at regular intervals, corrects any errors and rewrites them, and then performs the actual command. The purpose of the present invention is to provide a method for reducing errors that occur during execution.

te+ Structure and object of the invention According to the present invention, there is provided a control storage section for storing a microprogram, an address register for addressing the control storage section, and a control word read out from the control storage section. In a macro program control device having a data register, an error correction code logic mechanism that inputs the contents of the data register, detects and corrects errors, and a write register that holds data corrected by the error correction code logic mechanism. , a counter that can be incremented by at least +1, a connection bus for transferring the output of the counter to the address register, and a means for detecting that a specific control word has been read to the data register. When it is detected that the control word has been read out, the control word at the address indicated by the value maintained by the counter is read out, and if an error is detected in the read control word, the error is recognized as the above error. Corrected by correction code logic,
This is achieved by providing a method for controlling the above-mentioned control storage to be rewritten, at regular time intervals.
If a specific control word is read and checked and an error occurs, it can be corrected at that point, which has the effect of reducing errors that occur during actual execution of instructions.

<r+　Embodiments of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

The figure is a block diagram showing an embodiment of the present invention.

In the drawing, 1 is a control newt (CS) consisting of random access memory, 2 is an address register (AR), and 3 is a read register (RR).

31 is a flag bit that specifies a specific control word, 4 is a write register (WR), 5 is an error correction code logic (ECC) using an error correction code, and 6 is counted up in a micro operation cycle and is used to specify a specific control word. A counter whose initial value is cents or whose output can be blocked by means (
CONT), 7 is a control circuit.

First, a special diagnostic command is generated at regular time intervals (for example, the time interval of an interval timer), and the operating part of the command is written to the address register <AR) 2.
When the control memory (C3) 1 is accessed, a specific control word is read into the read register (RR) 3, and a flag 31 indicating that it is a specific control word is detected,
The control circuit 7 has insufficient starting power for diagnosis. At this time, if the control circuit 7 is stopped, it accepts this activation and starts the diagnostic operation, but if it is already in operation, the activation is invalidated.

When the control circuit 7 accepts the start-up, the control circuit 7 sets the state of the data processing device to a diagnostic state, and invalidates interface signals generated by the microprogram to other devices (or units).

The control circuit 7 is a counter (CONT) 6 wo+
1, transfers the value to the address register (Al1) 2, accesses the control memory (C5) 1, and transfers the control word read to the read register (RR) 3 to the error correction code logic (ECC). In 5, I will check.

At this time, if there is no error, the control circuit 7 writes all "0"s to the address register (/III2), reads the control word (non-operation command) at address 0, puts the data processing device in a waiting state, and then , cancels the diagnostic state, sends a diagnostic end signal to an instruction control unit (not shown), and requests the next instruction.

If an error is detected, the error correction code logic (
ECC〉5, the control word is modified, the modified data is set in the write register (row) 4, and the control word is stored in the control memory.
(C5) Rewrite to 1, write all aO" to f&, address register (AR) 2, read the control word at address O, release the diagnostic state, and then write the instruction control unit node ( A diagnosis end signal and a system automatic recovery signal (a signal that notifies the software that a hardware failure has occurred but that the hardware has automatically recovered from the failure) are sent to the system (not shown).

When the instruction control unit receives the system automatic recovery signal, it moves to interrupt processing, identifies that hardware abatement has occurred but has been automatically restored, and moves to the original processing.

The above operation is repeated at fixed time intervals of the interval timer, and the counter (CONT) 6 is incremented by 1 each time, so that all control words are read out and checked within a specific time. If an error occurs, it will continue to be corrected at that point.
Sufficient preventive maintenance effects can be obtained.

The automatic error correction mechanism using ECC is limited to 1-bit errors and cannot correct 2-bit errors, but
The probability of this case occurring is extremely low, so it is not a problem if ignored in reality, but it can be dealt with by duplicating and switching the control memories, for example, so it does not become a factor that hinders the implementation of the present invention. .

fg+ Effects of the Invention As explained in detail above, according to the present invention, the control memory (C5) is diagnosed at regular time intervals, and if an error occurs, the contents of the control memory are corrected at that point. This has the effect of reducing the probability that an error will occur in the control memory at the stage of executing actual instructions (except for maintenance instructions) and improving the reliability of the data processing device.

[Brief explanation of drawings]

The figure is a block diagram showing an embodiment of the present invention. In the drawing, ■ is the control memory (C5), 2 is the address register (AR), and 3 is the read register (R1).
? ), 31 is the flag bit, 4 is the write register (WR), 5 is the error correction code logic (ECC)
, 6 represents a counter (CONT), and 7 represents a control circuit, respectively. Small “o”

Claims (1)

[Claims] a control storage section that stores a microprogram, an address register that addresses the control storage section, and a data register that holds a control word read from the control storage section;
In a microprogram control device having an error correction code logic mechanism for inputting the contents of the data register to detect and correct errors, and a write register for holding data corrected by the error correction code logic mechanism, at least
A counter capable of incrementing by one, a connection for transferring the output of the counter to the address register, and means for detecting that a specific control word has been read to the data register are provided, When it is detected that the control word has been read out, the control word at the address indicated by the value obtained by incrementing the counter is read out, and if an error is detected in the read control word, the error is corrected as described above. A microprogram control device, characterized in that it is controlled to be corrected by an error correction code logic mechanism and rewritten to the control storage unit.