JPS602948A - Etching method - Google Patents

Etching method

Info

Publication number
JPS602948A
JPS602948A JP10913583A JP10913583A JPS602948A JP S602948 A JPS602948 A JP S602948A JP 10913583 A JP10913583 A JP 10913583A JP 10913583 A JP10913583 A JP 10913583A JP S602948 A JPS602948 A JP S602948A
Authority
JP
Japan
Prior art keywords
etching
photoresist
pattern
substrate
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10913583A
Other languages
Japanese (ja)
Inventor
Takuji Horio
堀尾 卓司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP10913583A priority Critical patent/JPS602948A/en
Publication of JPS602948A publication Critical patent/JPS602948A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004Photosensitive materials
    • G03F7/09Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/094Multilayer resist systems, e.g. planarising layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

PURPOSE:To control easily the angle of a taper only by a change in the thickness of a photosensitive resin without changing etching conditions by taperingly etching a substrate by making use of the thermal deformation of the photosensitive resin as an etching mask. CONSTITUTION:A thermally oxidized film 12 is grown on a silicon single crystal substrate 11. The film 12 is coated with a photoresist 13, and a photoresist pattern 13' is formed in a conventional photolithographic stage. The film 12 is etched through the pattern 13' as a mask to form a pattern 12' having the same shape as the pattern 13'. The substrate 11 is then etched through the patterns 12', 13' as a mask. During the etching, the photoresist undergoes thermal deformation and flows toward the side wall of the etched part. The substrate 11 is taperingly grooved 14 by continuing the etching while covering the side wall of the etched part with the flowing photoresist.

Description

【発明の詳細な説明】 (技術分野) この発明は、単結晶シリコン基板にテーパエツチングを
施すエツチング方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an etching method for performing taper etching on a single crystal silicon substrate.

(従来技術) 最も一般的な素子能動領域の分離法を第1図を参照して
説明する。
(Prior Art) The most common device active region separation method will be explained with reference to FIG.

まず、単結晶シリコン基板l上にシリコン酸化膜2を形
成した後、これを通常のホトリソ工程でノリーニングす
る(第1図(a))。
First, a silicon oxide film 2 is formed on a single-crystal silicon substrate 1, and then subjected to a normal photolithography process (FIG. 1(a)).

次に、そのバターニングされたシリコン酸化膜2をエツ
チングマスクとしてシリコン基板1を垂直に堀シ込み、
溝3を形成する(側1図(b))。
Next, using the patterned silicon oxide film 2 as an etching mask, the silicon substrate 1 is etched vertically.
A groove 3 is formed (side 1 figure (b)).

次に、そのff’j: 3の内壁にシリコン酸化膜4を
成長させた後、多結晶シリコン5を溝3に埋め込む。
Next, after growing a silicon oxide film 4 on the inner wall of the ff'j: 3, polycrystalline silicon 5 is buried in the groove 3.

さらに、熱酸化して多結晶シリコン5の表面部にシリコ
ン酸化膜6を形成する。(第1図(C))しかる後、シ
リコン酸化膜2と6の膜厚差を利用してシリコン酸化膜
2のみを取ル除く(第1図(d))。このシリコン酸化
膜2の除去によシ露出したシリコン基板部が5間の分離
領域(シリコン酸化膜6と多結晶シリコン5からなる)
によシ互いに分離された素子能動領域7である。
Further, a silicon oxide film 6 is formed on the surface of the polycrystalline silicon 5 by thermal oxidation. (FIG. 1(C)) Thereafter, only the silicon oxide film 2 is removed by utilizing the difference in thickness between the silicon oxide films 2 and 6 (FIG. 1(d)). By removing this silicon oxide film 2, the silicon substrate portion exposed is a separation region between 5 (consisting of silicon oxide film 6 and polycrystalline silicon 5).
The device active regions 7 are separated from each other.

しかるに、このような分離法では、多結晶シリコン5を
熱酸化する工程で、酸化による多結晶シリコンの体積膨
張のためにシリコン基板IK応力が生じるため、素子能
動領域7の部分に結晶欠陥が生じて、トランジスタ特性
を悪化させるという問題がある。
However, in such a separation method, in the step of thermally oxidizing polycrystalline silicon 5, silicon substrate IK stress is generated due to the volume expansion of polycrystalline silicon due to oxidation, so crystal defects are generated in the element active region 7. Therefore, there is a problem that transistor characteristics are deteriorated.

この問題を解決するためには、多結晶シリコン5を埋め
込む#3をテーパ状として、その斜面で体積膨張圧よる
応力を緩和することが必要である。
In order to solve this problem, it is necessary to make #3 into which the polycrystalline silicon 5 is embedded into a tapered shape so that the stress caused by the volumetric expansion pressure can be alleviated by its slope.

そのためには、シリコン基板1をテーパエツチングする
必要が1ハそれにはエツチング工程でガス種、ガス流1
1.圧力、RF電力などの条件を変更することが必要と
なるが、これらの条件を変更するとエツチング速度、均
一性1選択比なども変わってしまうので、それぞれのデ
バイスによって異ったテーパ角(斜面の角度)が必要な
場合、エツチング条件の選定が極めて困難であった。
To do this, it is necessary to taper-etch the silicon substrate 1, which involves changing the type of gas and the gas flow in the etching process.
1. It is necessary to change conditions such as pressure and RF power, but changing these conditions also changes etching speed, uniformity 1 selectivity, etc. When etching angle) is required, it is extremely difficult to select etching conditions.

(発明の目的) この発明は上記の点に@みなされたもので、同一のエツ
チング装置でエツチング条件を変更せずにテーパ角を制
御することができるエツチング方法を提供することを目
的とする。
(Object of the Invention) The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide an etching method in which the taper angle can be controlled using the same etching apparatus without changing the etching conditions.

(実施例) 以下この発明の一実施例を第2図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.

第2図(a)において、11は表面が(100)の単結
晶シリコン基板であシ、まず、この基板ll上に約15
00X厚に熱酸化膜12を成長させる。
In FIG. 2(a), 11 is a single crystal silicon substrate with a (100) surface.First, about 15
A thermal oxide film 12 is grown to a thickness of 00X.

さらに、その熱酸化膜12上に約1・5μm厚にホトレ
ジスト(たとえばマイクロポジット1400−17)1
3を塗布する。(第2図(a))しかる後、ホトレジス
ト13を通常のホトリソ工程でホトレジストパターン(
感元性樹脂層の)やターン) 13’とする。次に、そ
のホトレジストパターン13′をマスクとして熱酸化膜
12をエツチングすることKより、この熱酸化膜12を
ホトレノストパターン13’と同一の熱酸化膜ノやター
ン] 2’とする。(第2図0))) 次に、熱酸化膜・リーン12′とホトレジストパターン
13′をエツチングマスクツやターンとして単結晶シリ
コン基板11を約1μmエツチングする。
Furthermore, on the thermal oxide film 12, a photoresist (for example, Microposit 1400-17) 1 is applied to a thickness of about 1.5 μm.
Apply 3. (FIG. 2(a)) After that, the photoresist 13 is applied to the photoresist pattern (
) and turn) of the sensitive resin layer 13'. Next, the thermal oxide film 12 is etched using the photoresist pattern 13' as a mask, thereby forming the thermal oxide film 12 into the same thermal oxide film pattern 2' as the photoresist pattern 13'. (FIG. 20)) Next, the single crystal silicon substrate 11 is etched by about 1 μm using the thermal oxide film/lean 12' and the photoresist pattern 13' as an etching mask or turn.

ここで、エツチングは、平行平板型ドライエツチング装
置を用いて、四塩化炭素ガス50 SCCM*圧力0.
ITorr、高周波電源周波1400KHz、高周波電
流3Aの条件で行う。すると、エツチング中にホトレジ
ストパターン13′のホトレジストが熱変形してエツチ
ング部の側壁に流れ出し、これがエツチングマスクとな
る。このように、流れ出たホトレジストでエツチング部
の側壁を覆いつつエツチングを進めることによシ、この
場合は、第2図(C)に示すようにテーノJ?状の溝1
4が基板11に形成される。
Here, etching was performed using a parallel plate type dry etching apparatus using carbon tetrachloride gas of 50 SCCM*pressure of 0.
The test was conducted under the conditions of ITorr, high frequency power supply frequency of 1400 KHz, and high frequency current of 3 A. Then, during etching, the photoresist of the photoresist pattern 13' is thermally deformed and flows out onto the side wall of the etched area, which becomes an etching mask. In this way, by proceeding with etching while covering the side wall of the etched area with the flowed out photoresist, in this case, as shown in FIG. shaped groove 1
4 is formed on the substrate 11.

しかる後、過酸化水素水と硫酸の混合溶液(混合比HJ
 04 ’ H20t = 4 : 1 )に30分間
浸し、ホトレゾストパターン13′を除去する。以上に
よシ、素子能動領域が熱酸化膜(熱酸化膜パターン12
′)で保護され、素子分離領域がテーパエツチングされ
た構造物が形成される。(第2図(d))以上のように
一実施例では、ホトレジストの熱変形を利用してテーパ
のついたエツチングを行った。すなわち、’l′−行平
板型ドライエツチング装置を用いた、四塩化炭素ガス5
08CCM、圧力0.ITorr、高周波電流3.OA
の条件のエツチングでは、エツチングマスクが熱酸化膜
のみの場合、単結晶を垂直(テーパ角90°)にエツチ
ングするが、エツチングマスクとして熱酸化膜の上にホ
トレジストを乗せることにより、テーパのついたエツチ
ングを行うことができる。そして、このテーパ角は第3
図に示すようにホトレノスト膜厚を変えること例よって
制御でき、ガス抽、jス流量、ガス圧力、高周波電力を
変更する必要がないので、一台の装置で各種のデバイス
を処理し、それぞれのデバイスが異なったテーパ角の溝
を必要とするときには非常に有効である。
After that, a mixed solution of hydrogen peroxide and sulfuric acid (mixing ratio HJ
04'H20t=4:1) for 30 minutes to remove the photoresist pattern 13'. According to the above, the element active area is covered with a thermal oxide film (thermal oxide film pattern 12).
'), and a structure is formed in which the element isolation region is tapered etched. (FIG. 2(d)) As described above, in one embodiment, tapered etching was performed using thermal deformation of the photoresist. That is, carbon tetrachloride gas 5 was
08CCM, pressure 0. ITorr, high frequency current3. OA
In etching under these conditions, if the etching mask is only a thermal oxide film, the single crystal is etched vertically (taper angle 90°), but by placing photoresist on the thermal oxide film as an etching mask, a tapered Etching can be performed. And this taper angle is the third
As shown in the figure, changing the photorenost film thickness can be easily controlled, and there is no need to change gas extraction, gas flow rate, gas pressure, or high-frequency power, so one device can process various devices and each This is very useful when the device requires grooves with different taper angles.

(発明の効果) 以上詳述したようにこの発明のエツチング方法によれば
、エツチングマスクとしての感元性樹脂の熱変形を利用
して基板をチーツクエツチングするようにしたので、エ
ツチング条件の変更にたよらず、感元性樹脂の厚さを変
えるだけで容易にテーノ9角を制御できる。
(Effects of the Invention) As detailed above, according to the etching method of the present invention, since the substrate is chip-etched using thermal deformation of the sensitive resin as an etching mask, it is possible to change the etching conditions. The tenor angle can be easily controlled by simply changing the thickness of the sensitive resin.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は一般的な素子能動領域の分離法を説明するため
の断面図、第2図はこの発明のエツチング方法の一実施
例を説、明するための断面図、第3図はホトレノスト膜
厚とテーパ角の関係を示す特性図でちる。 11・・・単結晶シリコン基板、12^・・熱酸化膜。 12′・・・熱酸化膜パターン、13・・・ホトレジス
ト。 13’・・・ホトレジストパターン、14・・・溝。 特許出願人 沖電気工業株式会社 b(シ 1 鳳 第2図
FIG. 1 is a sectional view for explaining a general device active region separation method, FIG. 2 is a sectional view for explaining an embodiment of the etching method of the present invention, and FIG. 3 is a photorenost film. A characteristic diagram showing the relationship between thickness and taper angle. 11... Single crystal silicon substrate, 12^... Thermal oxide film. 12'...Thermal oxide film pattern, 13...Photoresist. 13'... Photoresist pattern, 14... Groove. Patent applicant: Oki Electric Industry Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 単結晶シリコン基板上に感光性樹脂層を含むエツチング
マスクツ臂ターンを形成する工程と、そのノやターンを
エツチングマスクとして感光性樹脂を熱変形しつつ基板
をテーパエツチングする工程とを具備してなるエツチン
グ方法。
The method comprises a step of forming an etching mask arm turn including a photosensitive resin layer on a single crystal silicon substrate, and a step of taper etching the substrate while thermally deforming the photosensitive resin using the turn or turn as an etching mask. An etching method.
JP10913583A 1983-06-20 1983-06-20 Etching method Pending JPS602948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10913583A JPS602948A (en) 1983-06-20 1983-06-20 Etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10913583A JPS602948A (en) 1983-06-20 1983-06-20 Etching method

Publications (1)

Publication Number Publication Date
JPS602948A true JPS602948A (en) 1985-01-09

Family

ID=14502467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10913583A Pending JPS602948A (en) 1983-06-20 1983-06-20 Etching method

Country Status (1)

Country Link
JP (1) JPS602948A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63157458U (en) * 1987-03-31 1988-10-14
EP0614215A1 (en) * 1993-03-05 1994-09-07 Alcatel N.V. Process for forming a metal contact on a relief of a semicondactor substrate, including a step of flowing a photosensitive resin layer
US6707107B2 (en) 2000-06-26 2004-03-16 Nec Lcd Technologies, Ltd. Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern
JP2007123781A (en) * 2005-10-31 2007-05-17 Toshiba Corp Semiconductor substrate with alignment mark and method for manufacturing alignment mark
EP2487793A1 (en) * 2011-02-11 2012-08-15 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Method for manufacturing an acoustic device including a phononic-crystal structure with cone-shaped inclusions which determine a stop band of the acoustic device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63157458U (en) * 1987-03-31 1988-10-14
EP0614215A1 (en) * 1993-03-05 1994-09-07 Alcatel N.V. Process for forming a metal contact on a relief of a semicondactor substrate, including a step of flowing a photosensitive resin layer
FR2702306A1 (en) * 1993-03-05 1994-09-09 Alcatel Nv Method of self-aligning a metal contact on a substrate of semiconductor material
US6953976B2 (en) 2000-06-26 2005-10-11 Nec Lcd Technologies, Ltd. Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern
US6791145B2 (en) 2000-06-26 2004-09-14 Nec Lcd Technologies, Ltd. Semiconductor device formed by utilizing deformed pattern
US6949766B2 (en) 2000-06-26 2005-09-27 Nec Lcd Technologies, Ltd. Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern
US6707107B2 (en) 2000-06-26 2004-03-16 Nec Lcd Technologies, Ltd. Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern
US6977422B2 (en) 2000-06-26 2005-12-20 Nec Lcd Technologies, Ltd. Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern
US7030467B2 (en) 2000-06-26 2006-04-18 Nec Lcd Technologies, Ltd. Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern
US7060623B2 (en) 2000-06-26 2006-06-13 Nec Lcd Technologies, Ltd. Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern
US7554164B2 (en) 2000-06-26 2009-06-30 Nec Lcd Technologies, Ltd. Semiconductor device having a gap between a gate electrode and a dummy gate electrode
JP2007123781A (en) * 2005-10-31 2007-05-17 Toshiba Corp Semiconductor substrate with alignment mark and method for manufacturing alignment mark
EP2487793A1 (en) * 2011-02-11 2012-08-15 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Method for manufacturing an acoustic device including a phononic-crystal structure with cone-shaped inclusions which determine a stop band of the acoustic device

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