JPS6028446B2 - amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in push-pull amplifier circuits using FETs and bipolar transistors.

Conventionally, buffer amplifiers have been proposed in which push-pull amplifiers are configured using FETs and bipolar transistors, but conventional buffer amplifiers of this type have the disadvantage that distortion increases as the signal source impedance increases, and dynamic In order to increase the range, it is necessary to increase the DC power supply voltage, which increases the gate leakage current of the FET, and therefore it is necessary to insert a coupling capacitor in the input section. The presence of such a coupling capacitor causes deterioration of frequency characteristics and impairs the high fidelity characteristics of the buffer amplifier. The present invention is applied to a push-pull buffer amplifier consisting of the conventional FET and bipolar transistor described above.
The conventional method described above can be achieved by cascading another bipolar transistor to T and applying a part of the output provided by the push-pull buffer amplifier to the base of the cascaded bipolar transistor. It is an attempt to eliminate defects.

The basic configuration will be explained below based on FIG.

In other words, in Fig. 1, Q represents an FET, and this FE
The gate of TQ is connected to the input terminal IN, and the source is connected via the capacitor C to the output terminal OUT.
Q2 is a bipolar transistor that constitutes a push-pull amplifier circuit together with the above-mentioned FETQ, and its base is the above-mentioned FETQ. The gates of FETQ and INI are connected together, and the emitter is connected to the source of FETQ through resistor R2.
Moreover, the collector is connected to the negative power supply -B. Q is F above
By connecting its emitter to the drain of ETQ, and connecting its collector to the positive power supply +B, the above FE
It is a bipolar transistor connected in cascade to TQ, and its base is connected to the positive power supply +B and FETQ,
Two resistors R3 and R4 connected in series with the source of
A Pootstrap circuit is constructed by connecting to the connection point b. When a signal is applied to the input terminal in the above configuration, FETQ and bipolar transistor Q2 mutually perform push-pull amplification, and the input signal is a
It appears at the homologous level at the point. This signal is connected to resistor R3 and R
The signal is divided by 4 and applied at point b, that is, to the base of the bipolar transistor Q connected in cascade to the FETQ. Therefore, the signal applied to the base of bipolar transistor Q3 is
Since the voltage is applied to the drain of FETQ, rather than the emitter of FETQ. The potentials of the gate, source, and drain of will change in phase with the input signal. Note that the gate-drain voltage of FETQ is calculated from the voltage at point b, which is obtained by dividing the voltage between point a and the positive power source 1B by resistors R3 and R4, to the base-emitter voltage (0.6V) of bipolar transistor Q3.
and FETQ. is the potential difference with the gate of
Therefore, if the state of R3 and R4 is set, the gate of FETQ,
The voltage across the drain is reduced, and gate leakage current can be eliminated. Figure 2 shows an example of a practical circuit of the proposed circuit, and the difference from the one in Figure 1 is that the FET
Q, to Q, . 〜Q, n are connected in parallel, bipolar transistor Q2 is connected in Darlington as shown as Q2, , Q22, and resistor R3 is connected in parallel as shown by Q2, , R.
32, and a coupling capacitor C' is inserted between the dividing point and point a.

Furthermore, Fig. 3 shows another practical circuit array of the present invention.
The difference from the one in Figure 2 is that a series circuit consisting of a resistor R6, a bipolar transistor Q4, and a variable resistor VR is inserted between the positive power supply +B and the negative power supply -B, and the base of the bipolar transistor Q4 is connected to the base of the bipolar transistor Q4. The base current of the bipolar transistor Q22 is sucked by the bipolar transistor Q, so that no voltage is applied to the input terminal IN. . In the amplifier of the present invention, a bipolar transistor is cascade-connected to one FET that performs push-pull amplification as described above, and a bootstrap circuit is configured.
The voltage between the drains can be reduced, and the gate leakage current can be reduced to zero.

Therefore, there is no need to insert a coupling capacitor into the input terminal, and the presence of the input coupling capacitor does not cause deterioration in frequency characteristics. Furthermore, since the gate leakage current can be reduced to zero or small, it is also possible to increase the power supply voltage and widen the dynamic range.

[Brief explanation of the drawing]

The drawings all show embodiments of the present invention; Fig. 1 is a wiring diagram showing the basic configuration, Fig. 2 is a wiring diagram showing a practical configuration, and Fig. 3 is a wiring diagram showing other practical configurations. FIG. Q・,QII～Q・n,. ,...FET, Q2, Q21,
Q Shigeru,. ,...bipolar transistor, Q...cascaded bipolar transistor. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. In an amplifier configured as a push-pull amplifier circuit by connecting the source of the FET and the emitter of the bipolar transistor in common, and outputting the output from this common connection point,
A bipolar transistor is cascaded between the drain of the FET and the power supply, and a part of the output signal in phase with the input signal provided by the push-pull amplifier circuit is applied to the base of the cascaded bipolar transistor. An amplifier featuring: