JPS6117408B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplifier having a push-pull configuration in all stages using field effect transistors (hereinafter referred to as FETs) of different polarities in the first stage.

This type of push-pull amplifier is characterized in that the complementary symmetry of the amplifier circuit cancels out distortion components generated within the circuit, resulting in an amplifier with low distortion.

However, when a FET is used in the first stage, due to variations in the FET's I _DSS , the FET
The operating points of the active elements in the second and subsequent stages that are directly connected to the output point of the push-pull circuit vary, which causes the operating currents of the upper and lower parts of the push-pull circuit to differ, making it difficult to keep the output offset voltage constant. have.

An example of the conventional one is shown in Fig. 1, but in order to eliminate the above-mentioned disadvantages, an
It is necessary to configure the drain of Q ₁ and the drain of P-channel FET Q ₂ to be connected to positive and negative power supplies +B and -B via semi-fixed variable resistors VR ₁ and VR ₂ , respectively. and two variable resistors VR ₁ and
The operating current of the second-stage driver transistors Q ₃ , Q ₄ and the output transistors Q ₅ , Q ₆ directly connected thereto, and the output terminal using each of VR ₂
I am trying to adjust the OUT offset voltage. However, in such conventional devices, it is necessary to adjust each of the two variable resistors, which not only makes each adjustment troublesome, but also
In mass production, low efficiency due to the addition of adjustment processes results in increased product costs.

The present invention aims to eliminate the above-mentioned disadvantages in all-stage push-pull amplifiers using FETs in the switching stages, and to provide an amplifier that can obtain predetermined operating characteristics without adjustment. An explanation will be given based on an embodiment of the invention shown in FIG. Q ₁ and Q ₂ are N-channel and P-channel FETs whose respective gates are connected to each other and connected to the input terminal IN, and whose respective sources are mutually connected. The drain of N-channel FET Q ₁ is connected to a resistor. The drain of the P-channel FET Q ₂ is connected to the positive power supply +B via R ₁ and to the negative power supply -B via the resistor R ₂ .

The drain of the N-channel FET Q ₁ is connected to the base of the PNP driver transistor Q ₃ , and the drain of the P-channel FET Q ₂ is connected to the base of the NPN driver transistor Q ₄ .
Furthermore, the collectors of each driver transistor Q ₃ and Q ₄ are NPN and PNP type output transistors.
Directly connected to Q ₅ and Q ₆ , each emitter resistance
It is configured to provide an output signal to the output terminal OUT via R ₃ and R ₄ . Note that the series circuit of resistor _R5 and diode D connected between the respective collectors of transistors _Q3 and _Q4 is a well-known bias circuit for determining the idle current of the push-pull output stage. A resistor R ₆ coupled to the source of the FET and a resistor R ₇ coupled between the source and ground constitute a negative feedback circuit.

Next, the bases of transistors Q ₇ and Q ₈ are connected to each other, and the base and collector of one transistor Q ₈ are shorted, thereby forming a current mirror circuit and mutually forming a constant current circuit. . Similarly, the bases of transistors Q ₉ and Q ₁₀ are connected to each other, and the base and collector of one transistor Q ₁₀ are shorted to form a current mirror circuit, and they also form a constant current circuit. There is. and transistors Q ₈ and Q ₁₀
Both collectors are connected to the output terminal via resistors R ₈ and R ₉ .
OUT and further transistor Q ₇
and transistor _Q9 are both connected in cascode to the driver transistors _Q3 and _Q4 .

In the above configuration, when a signal is applied to the input terminal IN, the input signal is applied to the FETs Q ₁ and Q ₂ , the driver transistors Q ₃ and Q ₄ , and the output transistor.
It is amplified by a push-pull amplifier circuit consisting of Q ₅ and Q ₆ and provided to the output terminal OUT. On the other hand, at the output terminal OUT, the collectors of transistors Q ₈ and Q ₁₀ forming part of the current mirror circuit are connected to resistors R ₈ and
Since it is connected through _R9 , assuming that the offset voltage at the output terminal OUT moves, for example, in the positive direction, the collector current of transistor _Q8 becomes smaller compared to the collector current of transistor Q10, and therefore the collector current of transistor Q8 becomes smaller than that of transistor _Q10 . The collector current of _Q7 is also small compared to the collector current of transistor _Q9 . As a result, the base potential of the output transistor _Q5 is lowered, and the offset voltage at the output terminal OUT is also lowered. Therefore, the output offset voltage will settle to approximately ground potential.

If the offset voltage at the output end moves in the negative direction, the output offset voltage will rise due to the opposite effect to that described above, and as a result, the output offset voltage will settle to approximately the ground potential.

Since this invention is constructed as described above, even though FETs are used in the cutting stage, it is possible to suppress variations in the operating current in the second and subsequent stages that occur due to variations in the I _DSS of the FETs. and
Therefore, the output offset voltage can always be kept at approximately ground potential. Moreover, since the above effects can be achieved without adjusting the circuit, production efficiency can be increased in mass production, and it can also contribute to cost reduction.

[Brief explanation of the drawing]

Figure 1 is a wiring diagram of an amplifier showing a conventional example;
The figure is a wiring diagram showing an embodiment of the present invention. Q ₁ , Q ₂ ... field effect transistor, Q ₃ ~ _{Q 6} ...
…Push-pull amplification transistor, Q ₇ to Q ₁₀ …
...Current source transistor.

Claims (1)

[Claims] 1. In a push-pull amplifier that uses field-effect transistors of different polarities in the first stage, applies the same input signal to each gate of each field-effect transistor, push-pull amplifies the output of the field-effect transistor, and brings it to the output terminal. First and second driver transistors are connected to the drain of the effect transistor, and a current mirror circuit is configured between the first and second driver transistors and a + power source and a − power source, and a constant current circuit is configured with each other. and one end of the third and fourth transistor pairs are connected in cascade to the first and second driver transistors, and one end of each of the third and fourth transistor pairs is connected to the first and second driver transistors. A push-pull amplifier characterized in that one end of a pair of transistors is connected to an output end.