JPS5925483B2 - push pull amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a push-pull amplifier circuit used for output amplification of audio equipment.

These push-pull amplifier circuits are generally referred to as power amplifiers, and various types are employed, but the basic ones are class A and class B complementary push-pull amplifier circuits.

Class A transistors have a pair of output transistors that always operate in the active region and never shift to the cutoff region, so they have the advantage of not generating switching distortion. It is thick (there is a drawback).

On the other hand, class B transistors have less bias current and less heat loss than class A transistors, but switching distortion occurs because the output transistors are alternately cut off.

In view of these points, the present invention aims to eliminate the drawbacks of class A and class B push-pull amplifier circuits.

A push-pull amplifier circuit with low heat loss and no switching distortion is provided.

For this purpose, the present invention provides an N-channel transistor and a P-channel transistor, each having a first and a second output transistor whose emitters are connected in common at the output point through a resistor, respectively, and whose source is connected to a load resistor. Channel FE
The source of this FET is connected to the base of the output transistor, and the bias applied to each gate is set to approximately 1/2 IDs s, and when a signal input is applied to the gate of the FET, the The voltage between the bases of the first and second output transistors is changed in the direction of increasing, thereby compensating for the decrease in the voltage between the terminals of the emitter resistor of each one, thereby preventing the cutoff transition of the one output transistor. Features.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, the emitters of NPN) transistor 1 and PNP) transistor 1' as complementary output transistors each have a resistor of 2.2"'. It is commonly connected to the output point O via ¥, and is further connected to the load 3.

The base of transistor 1.1' is complementary FE
N-channel FET4 and P-channel FET as T
4' sources, respectively, and these FETs 4'
Resistors 5 and 5' are connected between the source of 4' and the power supply, respectively.

Transistors 1 and 1' are connected between both gates of FET4 and 4'.
A resistor 7 of a bias circuit 6 for flowing a bias current is connected to the resistor 7, and the resistor 7 is supplied with a high bias current by a constant current source 8.

Furthermore, a human-powered transistor 9 is connected to the bias circuit 6, and a signal from an input point S is applied to the base of the transistor 9.

The signal is transmitted to transistor 1゜1 through FET4, 4'.
' is applied to 'c1' and is push-pull amplified by the transistors 1 and 1' to drive the 'c1 load 3'.

Next, the operation of the push-pull amplifier circuit shown in Fig. 1 will be explained using Figs. 2 and 3. First, in a no-signal state, the FET
4. The operating point A and A are both set at point A in FIG. 2, that is, the point where the drain current is 0.5 IDss.

This is because FETs have square characteristics. The gate-source voltage VGS at this time is 0.29Vp.

When the output point O swings to the positive side due to the human input signal condition, the voltage across the resistor 2 increases, and the voltage VE2 across the resistor 2' decreases.

At this time, the connection point P between the source of the FET 4 and the resistor 5 also swings to the positive side, so the current flowing through the resistor 5 increases and the drain current of the FET 4 also increases.

-The connection point V between the source of FET 4' and resistor 5' also swings to the positive side, so the current flowing through resistor 5' decreases and FET 4
The drain current of ' also decreases.

At this time, the operating point of FET4 shifts from point A to point B in Figure 2, and the gate-source voltage changes from 0.29 Vp to O.13Vp, but the operating point of FET4' shifts from point A to point B in Figure 2.
The voltage between the gate and source becomes 0 as it moves from point A in the figure to point 0.
．． It changes from 29Vp to 0.5Vp.

Therefore, the voltage between the sources of FET4 and 4'. That is, the voltage VBB between the bases of transistors 1 and 1' is equal to the change in voltage between the gate and source of FET 4, 0.16Vp, and EFT 4'.
It changes by 0.05Vp, which is the difference between the gate-source voltage change amount of 0.21Vp, and this change is caused by
1' is in the direction of increasing the base-to-base voltage VBB.

This is in the direction of compensating for the decrease in the voltage v02 across the resistor 10, and as a result, it becomes possible to prevent the transistor 1' from switching off.

On the other hand, when the output point 0 swings to the negative side due to the input signal condition, VBB on the interbase layer of the FET 4° 4' similarly increases, and the cutoff transition of the transistor 1 is prevented.

In Fig. 3, D indicates the output voltage waveform, and E indicates the FE
T4.4' source voltage, i.e. transistors 1,1'
The waveform of the base-to-base voltage vBB is shown.

Therefore, as shown in FIG. 4, the current a of transistor 1 and the current a' of transistor 1' never become zero (they can always operate in the active region, and the idle current when there is no signal is A). It is possible to make the amplifier circuit sufficiently small compared to a class amplifier circuit.

In the figure, broken lines S and b' indicate current waveforms of a conventional class B push-pull amplifier circuit, and CTC' indicates an idle current waveform when there is no signal.

Thus, according to the invention, the output transistor 1.1'
Since the amplifier always operates in the active region and never shifts to the cutoff region, switching distortion unlike in a class B amplifier circuit does not occur.

Furthermore, since there is no need to flow a large bias current, heat loss can be reduced compared to a class A amplifier circuit.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the push-pull amplifier circuit according to the present invention, Fig. 2 is a diagram of the operating characteristics of the FET, Fig. 3 is a diagram of the output voltage waveform and the voltage waveform between the base of the output transistor, and Fig. 4 is a current waveform diagram of the output transistor.

Claims (1)

[Claims] 1. A transistor having a first and a second output transistor whose emitters are connected in common at the output point via a resistor, and a load resistor is connected to each source.
The source of the FET is connected to the base of the output transistor, and the bias applied to each gate is set to a gate bias voltage corresponding to approximately 1/2 ID5s, and ID5s is the gate bias voltage. drain current when bias is zero), the above F
When a signal is applied to the gate of ET, the tEEE between the bases of the first and second output transistors is changed in the direction of increasing, and the decrease in the voltage between the terminals of the emitter resistor of each one is compensated for. A push-pull amplifier circuit characterized in that a cut-off transition of an output transistor is prevented.