JPS6027430B2 - microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a one-chip microcomputer, and more particularly to an output signal forming circuit that outputs the contents of a general-purpose register.

Subordinate microphone. For serial output from a computer, a data buffer such as a shift register is provided, and after data is set in this data buffer, the data is shifted one bit at a time for each clock and output, or the data is set in a general-purpose register, etc. A method of outputting this data using one bit of a parallel output terminal, setting the data in a general-purpose register again, and outputting the data has been explored. According to the former method, data output is very efficient, but there is a drawback that a data buffer must always be provided inside the melon 1, which increases the area of the LSI. According to this method, for example, 18 steps are normally required to perform a 9-bit serial output, and only 1 bit can be output for every 2 steps, resulting in a slow speed. The present invention provides a microcomputer that can efficiently derive serial output by eliminating the drawbacks of the conventional method described above.

The present invention will be explained in detail using the drawings. The figure is a block diagram of a melon 1 consisting of one chip according to the present invention, which includes a data memory for storing data, an arithmetic unit for performing arithmetic or logical operations on data stored in the data memory, an instruction memory for storing instructions, A program counter that addresses the instruction memory, a decoder that decodes instructions output from the instruction memory, and various registers that control the data memory, the arithmetic unit, and input/output terminals of the BI,
A clock signal from an oscillation circuit is applied as needed, and the introduced input signals are processed as appropriate to form signals for controlling the operation of the display or various devices.

In the figure, ACC and ACC2 are general-purpose first and second registers that are provided so that they can operate independently, and in this embodiment, they are composed of 4-bit registers, and function as an accumulator in normal operating conditions. do.

The ALU is an arithmetic unit that performs arithmetic or logical operations, and the operation is performed between an accumulator ACC, an accumulator ACC2, an accumulator ACC, or an accumulator ACC2, which will be described later, and a RAM (data memory), which will be described later, and an accumulator ACC, or an accumulator ACC2, which will be described later. It can be executed with ROM (instruction memory). A flip-flop C connected to the accumulator ACC has a function of holding a carry generated as a result of an operation, and serves as a carry flip-flop for the 1-bit component. C can be set and reset by a command.
The input terminals 1 to 4 are connected to the first register of the accumulator ACC, and the signals (data) given to the input terminals 1 to 4 are stored in the first register ACC by a command given from the ROM, which will be described later. . The input/output terminals 5 to 8 are connected to the second register of the accumulator ACC2, and data can be exchanged according to a command. Terminal 9 is provided in BI as an output terminal, and is connected inside melon 1 to 1 bit of a 4-bit general-purpose register constituting the second accumulator ACC2. The second accumulator ACC2 is the first accumulator ACC.
, and carry flip-flop. Between C, R to be described later
They are connected in series according to instructions from OM to form a register with 9-bit components. The contents of the combined 9-bit registers are shifted left or right with a shift instruction. Therefore, as for the output signal derived from the output terminal 9, the contents in the register are continuously taken out as a serial output, and any one bit can also be obtained as an LSI output. The RAM is a data memory that can exchange data with the accumulator ACC and the accumulator ACC2. Addressing of the data memory RAM is given from a register date and a register L consisting of 4 bits. Register date specifies the upper 4 bits, and register L specifies the lower 4 bits. In this embodiment, both P3 and P4 are composed of 4-bit registers, and data can be input to the accumulators ACC and ACC2 from either of them. Output terminals 10-13 and 14-
17 are terminals for outputting the contents of register P3 and register P4, respectively. SR and SR2 are stack registers that hold the contents of the program counter PC, and are registers that store the return address while the program counter PC specifies the subroutine address. Consists of registers. Terminal 18 connects BI to GND, and terminal 19 connects to power supply V blood. Next, the ROM is an instruction memory in which various instructions are stored in advance according to the functions of the microcomputer. In particular, in the present invention, the accumulator ACC, accumulator ACC2, and carrier IJ flip-flop C are combined to form a 9-bit shift register. The constituent instructions and instructions for sequentially shifting the contents of the 9-bit shift register to the left or right and outputting them to the output terminal 9 as appropriate are written, and these instructions are addressed and read by the program counter PC. The data stored in the accumulators ACC, , ACC2 and the carrier flip-flop in the output state are serially coupled, and a desired bit is taken out from the output terminal 9 as an LSI output through a shift operation according to an instruction. In this embodiment, a case has been described in which two accumulators and a carrier flip-flop are selected as registers to be combined.
Various instructions are given from the OM, and in conjunction with these instructions, serial output by register combination can be used more effectively.

However, the present invention can also be implemented using other registers provided within the LSI, such as output registers P3 and P4. The instructions read from the ROM are decoded by the instruction decoder ID and provided to each section of the LSI including the accumulator section.

Hereinafter, for at least two registers that operate independently as in the present invention, an output terminal is formed in one of the registers, and R
By writing and configuring the OM with instructions to connect these registers in advance and reading the instructions, it is possible to effectively utilize the general-purpose registers that are normally used for processing bit-length data of the register itself. Continuous serial output can be obtained even for signals consisting of bits longer than the bit length of the register itself, and a simple configuration is added without requiring a special occupied area as a circuit for serial output in the melon 1. LSI functionality can be significantly improved by only using the following methods.

[Brief explanation of drawings]

The figure is a main part block diagram showing an embodiment according to the present invention.

Claims (1)

[Claims] 1 A general-purpose first register and a second register independently provided in the same chip, an output terminal derived from one bit of either the first register or the second register, and the first register and a line that connects the second register in series, and control means that connects the first register and the second register via the connection line and gives a command to shift the signal, the first register Alternatively, a microcomputer is characterized in that it outputs the desired 1-bit content of the second register.