JPS58123121A - Input control circuit - Google Patents

Abstract

PURPOSE:To select plural kind of inputs and to store data in one kind of register by controlling inputs to the register by a control signal for switching and a clock signal. CONSTITUTION:When transferred data is inputted in parallel in response to a signal D and a clock signal is supplied, inputs to terminals C11-C14 are stored in registers B11-B14 through switching gates A11-A14 and outputs from the registers B11-B14 are stored in registers B15-B18 through switching gates A15-A18; and the same operation is performed in response to the 2nd clock signal and an 8-bit input is stored in eight registers. Then, when data transfer is placed in serial input mode by the signal D and the clock is supplied, outputs from the terminal C11, and registers B11-B17 are stored in the registers B11- B18 through the switching gates A11-A18 and an 8-bit input is stored in the eight registers by eight clock signals.

Description

[Detailed description of the invention] Zaokiri is related to the input control circuit. Conventionally, when transferring data between microcomputers, one bit is serially input one bit at a time, and one bit is input in parallel. J/(It was either to receive input. If you use this method, only 7 real inputs are possible, then when you interface with a chip that is capable of parallel transfer.

There will be waste on the ridge of the output chip. Conversely, if only parallel transfer is possible, there will be no chips and one interface capable of serial transfer. Furthermore, when a single chip has both functional metals, there is a drawback that the chip area becomes large.

It is an object of the present invention to eliminate the above-mentioned drawbacks and provide a more effective input control circuit for LiMl.

The input control circuit according to the present invention includes a switching gate that receives a switching control signal and a clock signal as input, a plurality of switching gates that use this output as a control signal, and four switching gates that each use this output as an input. It consists of a group of fixed registers, and register inputs are controlled by switching control signals and clock signals.

? This special feature is characterized in that f number of types of inputs are selected and the data is stored in registers of one elliptical class.The following is a description using this Genmeikaku drawing.

For convenience of the following explanation, it is assumed that the input register can switch between 8-bit, shift, serial input, and 4-bit parallel input.

In the block diagram shown in FIG. 1, A11.
...A18 is serial manual input and parallel input U
), H11+...B18 is a register that stores the outputs of All,...A18, and 11 is a register for switching between 7 real and parallel. Inputs the clock signal for data transfer and generates a signal for serial input or parallel input.
It is J road. If the data transfer is made into parallel input by the signal RI, and the RI signal is supplied.

Terminal C1t +CI2*(-'13+C14 input is switching gate A 11 * A 12 IA 13 t
At the end of A14.

Register B l l + Bl 2 IB 13 t
n stored in B14.

The output of register H12, tl13 and 8141 is transferred to B15 by passing the switching gate A15IA16IA17IA18.
The same thing happens with the second clock signal and the 8-bit input is stored in 8 registers. , when a clock signal is supplied, terminal C1x*register B11...
・The output of B17 can be switched individually.) Ails...
...through A18 to register B11.・・・・・・81
The 8-bit input is stored in 8 registers by 8 clock signals.

In this way, by controlling multiple human forces using switching gates and control signals, and storing data in one type of register, LSI12) Functional or chip stacking waste can be saved *LS IK is an effective circuit. be.

Next, FIG. 2 shows an embodiment of the present invention. In FIG. 2, 11 is a signal that is high when serial input is input, and low when parallel input is input. In the case of serial input, D is high and the clock is input. When the voltage becomes high, 1111°, the gate 23 becomes high, and the transfer gate A21,
A22 becomes the conductor and terminal C11*Resistor B11,・
...817 outputs are each A11l...A
B11 t...stored in B18 through 18 meetings n
, when the clock signal goes low, the output of gate 23 goes low, and transfer gate A21 . A22...
... becomes non-4-carrying, and the output of Kate 24 becomes No.1-i,
Transfer gates 821', 822/...
becomes conductive, and the input of terminal C1l is stored in register Bll. [The output of register B11y...B17 is stored in register #:312...B18 rL, 8
Eight bits of data are stored in eight registers with one clock signal. In the case of parallel input, when the signal υ is low and the clock becomes high, the output of gate 22 becomes high and transfer gate A21'...' R
II2 B' becomes conductive, +41, terminal Cl l *
C12s C13* Cl 4 *Register B l
The outputs of l r Bl 2- B 13 + B l 4 are transferred respectively)A21'...A28
'tA and stored in register B111...J8 When the clock signal becomes low, the output of gate 22 becomes low and transfer gate A21'tA
22'......it becomes non-conducting, and the output of gate 24 becomes 71, transfer gate)B21't.
...B28' becomes conductive and terminal C1IIC12I
C13IC14 input, register B129B1
The outputs of 3eB14 are transferred respectively)A21'・
...A28'? Through register 811...
... 8 bits stored in B18 with 3 or 2 clock signals,
data will be input.

In this way, by using the cutoff 9#uo14 and the control signal t-11', data can be inputted using only one type of register for inputs of the type 4Ia, which is effective for iMl.

[Brief explanation of drawings]

FIG. 81 is a circuit diagram showing a block diagram of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention. A11. ...A18...Switching circuit, Hll. ...B18...Register, C1l...C1
3...Input terminal, lJ...Control signal,
C1, ueK...read clock signal, 11
... Signal generation circuit, A21. ...A 28
s A 21"t...A28'tB21...H2B
, B21'...B28'...Transfer-Fs Gl hGl 2 *G13 + Gl
4-...C81*G82*u83*G84...
・Inverter, 22.23...ANL) Gate, 21°25...Inverter, 24...
Heuh game) C11 Ran 12. c13ran 14...
Input terminal. L f diagram

Claims (1)

[Claims] Inputs a signal to control the switch-14 and a clock signal! It has a group of control gates, several horizontal switching gates whose outputs are used as control signals, and several horizontal register groups whose outputs are each input. Control,? ! ft14f t"
I road.