JPS6225215B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an input control circuit.

Conventionally, when data is transferred between microcomputers, input is received either serially, one bit at a time, or several bits are input in parallel. When using this method, if only serial input is possible, when interfacing with a chip capable of parallel transfer,
Due to the function of the output chip, waste occurs. Conversely, if only parallel transfer is possible, it will not be possible to interface with a chip that is capable of serial transfer. Another drawback is that when a single chip has both functions, the chip area becomes large.

It is an object of the present invention to eliminate the above-mentioned drawbacks and provide an input control circuit that is more effective for LSI.

The input control circuit of the present invention includes a plurality of input terminals,
It has a plurality of gate circuits that are independently connected to each of the plurality of input terminals, and a plurality of registers that are provided corresponding to each gate circuit and whose input terminals are connected to the output terminals of the corresponding gate circuits. , each of the plurality of gate circuits includes a first switching gate that receives a first control signal and inputs a signal input from a corresponding input terminal to a corresponding register via the output terminal; a second switching gate that is provided independently of the switching gate of and responds to a second control signal, and only the second switching gate in the first stage gate circuit is connected to the input terminal, and the other gates are connected to the input terminal. Each second switching gate of the circuit is connected to the output terminal of the preceding register, and when the first control signal is applied, a signal is sent in parallel to each register via the first switching gate. and when the second control signal is applied, a signal is input in series from an input terminal connected to the second switching gate of the first stage gate circuit via the second switching gate to each register. It is characterized by serial input via the

This invention will be explained below using the drawings.

For convenience of the following explanation, the input register is assumed to be 8 bits, and the input register is switched between serial input and 4-bit parallel input.

In FIG. 1, a block diagram showing the configuration of the present invention, A11, . . . A18 are serial input and parallel input switching gates, and B11, .
11 is a register that stores the output of each of A11, . be. When data transfer is made into parallel input by signal D and a clock signal is supplied, the inputs of terminals C11, C12, C13, and C14 are connected to switching gates A11, A12, A13, and A1.
4, registers B11, B12, B13,
B14 and registers B11, B12, B
13, B14 outputs are switching gates A15, A
16, A17, A18 through B15, B16,
The second clock signal causes the same thing to happen and the 8-bit input is stored in 8 registers. Next, when data transfer is made into serial input by signal D and a clock signal is supplied, terminal C11, register B11...B17
The outputs of the switching gates A11, . . . A18 are respectively
The 8-bit input is stored in the 8 registers by 8 clock signals.

In this way, by controlling multiple input terminals using switching gates and control signals and storing data in one type of register, it is an effective circuit for LSIs because it eliminates waste in terms of LSI functionality and chip area.

Next, FIG. 2 shows an embodiment of the present invention. In FIG. 2, D is a signal that is high for serial input and low for parallel input. In the case of serial input, D is high and when the clock goes high, gate 23 goes high and transfer gate A
21,... _A22 become conductive, and the outputs of terminal C11, registers B11,...B17 become A11,..., respectively.
stored in B11,...B18 through A18,
When the clock signal goes low, the output of gate 23 goes low, and transfer gates A21 and A2
2,... become non-conductive, the output of gate 24 becomes high, and transfer gates B21', B22'...
... becomes conductive and the input of terminal C11 becomes register B1
1 and the outputs of registers B11, . . . B17 are stored in registers B12 . For parallel input,
When signal D is low and the clock goes high, gate 2
The output of transfer gate A2 becomes high.
1'...'A28' becomes conductive, and terminals C11 and C
12, C13, C14, register B11, B1
The outputs of 2, B13, and B14 are sent to register B1 through transfer gates A21'...A28', respectively.
1, . . . When the clock signal becomes low, the output of the gate 22 becomes low, the transfer gates A21', A22', . ' becomes conductive and terminal C1
1, C12, C13, C14 input, register B
The outputs of the registers B11, B12, B13, and B14 are stored in the registers B11...B18 through transfer gates A21'...A28', respectively, and 8-bit data is input with two clock signals. By using switching circuits and control signals in this way, data of multiple types of input can be input using only one type of register, making it an effective circuit for LSI.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a block diagram of the present invention;
The figure shows an embodiment of the present invention. A11,...A18...Switching circuit, B1
1,...B18...Register, C11...C13
...Input terminal, D...Control signal, CLOCK...Reading clock signal, 11...Signal generation circuit, A
21,...A28,A21',...A28',B2
1...B28, B21'...B28'...Transfer gate, G11, G12, G13, G14,
...G81, G82, G83, G84 ... Inverter, 22, 23 ... AND gate, 21, 25
...Inverter, 24...NOR gate, C1
1, C12, C13, C14...Input terminals.

Claims (1)

[Claims] 1 A plurality of input terminals, a plurality of gate circuits independently connected to each of the plurality of input terminals, and a plurality of gate circuits provided corresponding to each gate circuit, the input terminal being connected to the output terminal of the corresponding gate circuit. a plurality of registers, each of the plurality of gate circuits having a first
a first switching gate that receives a control signal and inputs a signal input from a corresponding input terminal to a corresponding register via the output terminal; and a second switching gate that is provided independently of the first switching gate. a second switching gate responsive to a control signal, only the second switching gate in the first stage gate circuit is connected to the input terminal, and each second switching gate of the other gate circuits is connected to the previous stage register. When the first control signal is applied, a signal is input to each register in parallel through the first switching gate, and when the second control signal is applied, a signal is input to each register in parallel. At times, a signal input in series from an input terminal connected to a second switching gate of the first stage gate circuit via a second switching gate is inputted in series via each register. control circuit.