JPS6387809A - Operational amplifier - Google Patents

Abstract

PURPOSE:To improve the offset adjusting accuracy by inputting a coded data in an offset adjusting circuit, using a decoder to select an N-channel transistor (TR) switch for the selection of the combination of resistive elements thereby decreasing number of inputs. CONSTITUTION:Plural resistive elements r1-rn are connected in series across offset adjusting terminals 2,3 of an operational amplifier 1 in the offset adjusting circuit, and the N-channel TR switches S1-Sn for selection are connected between a power supply and connecting point of the resistive elements r1-rn. Decoder outputs SG1-SGn are connected to gate inputs of the N-channel TR switches S1-Sn and outputs of logic elements I1-I4 are connected to the input of the decoder 8. In giving a code to an input of the logic elements, any of decoder outputs SG1-SGn goes to an H potential to turn on the N-channel TR switches S1-Sn thereby selecting the resistive elements r1-rn. Thus, number of inputs is minimized to the utmost and fine offset adjustment is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a &'knee operational amplifier, and specifically relates to an offset adjustment circuit in an operational amplifier.

[Conventional technology]

FIG. 2 shows an example of an offset adjustment circuit using a conventional selection transistor switch.

At both ends of the offset adjustment terminal 2.6 of the operational amplifier 1,
A plurality of resistance elements r1 to rn are connected in series to form a resistance element r.
, -rn and the power supply are connected to selection Nch transistor switches 8 to 11, and the gate of the Neh transistor switch is connected to the output of the logic element FIn. When an L potential is input to the input of any one of the logic elements 11 to In, the output of the logic element becomes H, and the output selects a resistance element by turning on the NCh transistor switch. At this time, adjust the NC so that the currents flowing through offset adjustment terminals 2 and 3 become equal at points 4 or 5 between the resistor elements connected in series.
Offset adjustment is performed by selecting h transistor switches 81 to Sn.

[Problem that the invention seeks to solve]

When performing precise offset adjustment using this conventional method,
It is necessary to increase the number of resistive elements and make the division value finer.

At this time, as the number of resistance elements increases, the number of logic elements also increases, and as a result, the number of inputs to the logic elements increases.

Therefore, if it is constructed on a semiconductor integrated circuit, the semiconductor integrated circuit will become large due to the large number of wiring lines.

Therefore, it is not suitable for configuring on a semiconductor integrated circuit.

The purpose of the present invention is to reduce the number of inputs of logic elements.
An object of the present invention is to provide an operational amplifier suitable for configuring on a semiconductor integrated circuit while minimizing the number of wiring lines. By inserting a decoder between the gate input of the Nch transistor switch that selects the resistance element and the output of the logic element, inputting coded data, and selecting the Bf decoder Nch transistor switch, the combination of the resistance elements is determined. This is the choice.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 shows an offset adjustment circuit using a selection transistor switch and a decoder showing one embodiment of the present invention.

At both ends of the offset adjustment terminal 2 of the operational amplifier 1,
A plurality of resistance elements r1 to rn are connected in series, and a selection Nch transistor switch M to S is connected between each connection point between resistance elements r, to rn and a power supply, and the Nch,
,,) To the transistor switch ~SL1, decoder outputs SQt~SG are connected to the gate input, and outputs of logic elements I8~L are connected to the input of the decoder.

When you input the code at the inputs D1 to D4 of the logic element,
When one of the decoder outputs SG, -SGn becomes H potential, the NCh transistor switches 81 - S11 are turned on to select a resistance element.

At this time, the offset adjustment is performed by selecting the NCh transistor switch so that the currents flowing through the offset adjustment terminals 2 and 3 of the operational amplifier 1 are equal at the connection point between the resistive elements. In addition, in order to improve the accuracy of offset adjustment, it is sufficient to reduce the resistance value of resistor element r and increase the number of resistor elements r.
t 16 letters') I) By setting the location to 5 bits, 32 selections can be made and accuracy can be easily improved.

The neh) transistor inch used in carrying out the present invention can also be realized by a peh) transistor switch or a mechanical switch.

〔Effect of the invention〕

As is clear from the above explanation, if the present invention is used, 4 bits
The decoder allows 16 selections, and the 5-bit decoder allows 32 selections, making it possible to achieve fine offset adjustment by minimizing the number of inputs.

Furthermore, by inputting coded offset data from another semiconductor integrated circuit to the offset input of the semiconductor integrated circuit using the present invention, it is also possible to control the offset by the other semiconductor integrated circuit. It can be effectively used in various analog circuits or semiconductor integrated circuits with a mixture of digital and analog.

[Brief explanation of the drawing]

FIG. 1 is an offset adjustment circuit diagram using a decoder showing an embodiment of the present invention, and FIG. 2 is a conventional offset adjustment circuit diagram. 1...Operation amplifier, 2.6...Offset adjustment terminal, S, , S
2~3n...Nch transistor, rl, r
2~rn...Resistance element, 8...Decoder, SG,, SG2~SG,...Decoder output. So second eye

Claims (1)

[Claims] In a differential amplifier circuit of an operational amplifier, a plurality of resistive elements connected in series are connected between the source electrodes of two transistors constituting a load transistor of the differential amplifier circuit, and each connection point between the resistive elements. It consists of a selection switch connected between the power supply and a decoder that selects the switch,
An operational amplifier characterized in that offset adjustment of a differential amplifier circuit of the operational amplifier is performed.