JPS6027295A - Time switch - Google Patents

Abstract

PURPOSE:To facilitate designing and producing a switch by providing two decoders independent of each other for write and read in a data bus memory to drive the time switch in a speed equivalent to the multiplicity of input/output highways. CONSTITUTION:A data bus memory 10' having two independent address input ports Ain and Aout of a write address WA and a read address RA is used, and sequential write and random read are performed. Two address decoders are prepared in the data bus memory 10', and write and read are executed independently of each other in accordance with information given from a write counter 20 and a read control memory 30. When the multiplicity of the time switch is (n) for input and output, it is sufficient if the data bus memory 10' is operated in a speed equivalent to the multiplicity because write and read are executed independently of each other, and thus, design and production of the switch are made easy.

Description

[Detailed description of the invention] The present invention relates to a time switch for a time division exchange.

Conventionally, the time switch of a one-time division switch was usually constructed using a general-purpose memory.

In this case, in general, a time switch with n multiple inputs and 1 m multiple outputs has n write cycles and n write cycles per frame period.
One frame period is divided into n0m cycles for reading and writing. Consequently, it is an object of the present invention to overcome the above-mentioned drawbacks of the prior art.

An object of the present invention is to provide a time switch capable of simultaneously and independently writing an input signal and reading an output signal.

According to the present invention, a data bus memory, which is a time switch element of a time division switch, has two sets of decoders: a write address decoder for selecting a write address, and a read address decoder for selecting a read address. A time switch with two sets of address input ports is obtained.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of the configuration of a conventional time switch, in which a conventional data bus memory 10 is configured with a general-purpose memory. This shows a so-called sequential write/random read time switch. In the general-purpose memory 10, only one set of address input terminals A is prepared.

) 11 included counter 20 output WA and read control memory 60
A multiplex circuit 40 is provided which inputs the output RA of.

Writing and reading are performed according to cycled write and read timings.

FIG. 2 shows a configuration example of an embodiment of the time switch according to the present invention, which uses a data bus memory 10' having two independent address input ports Ain and Aout, a write address WA and a read address RA. , similar to the conventional example shown in FIG. 1, sequential writing and random reading are performed. Inside the data bus memory 10', two types of address decoders, which will be described in detail later, are prepared, and according to the information scooped from the write counter 20 and the read control memory 50, 111
reading and writing are executed independently.

Here, if the multiplicity of the 1-hour switch is n for both input and output, then in the conventional method (Fig. 1), 2 times per frame period.
It is necessary to perform n accesses (write and read),
While the data bus memory 10 is required to have a speed twice as high as the multiplicity, in the embodiment according to the present invention (FIG. 2), since writing and reading are performed independently, the data bus memory 10
0' may operate at a speed comparable to the multiplicity, and has the advantage that the switch can be easily designed and manufactured.

Figure 6 shows the data bus memo IJ10' shown in Figure 2.
An example of the configuration is shown in more detail. input highway (
Write data WD inputted from FIG. 2) is written into the memory cell 13 selected by the write address decoder 11.

On the other hand, independently of this, the contents of the memory cells 16 specified by the read address decoder 12 are sequentially outputted from the output highway (FIG. 2) as read data WD.

FIG. 4 shows an example of the configuration of the memory cell 1 shown in FIG. 6 in more detail. In this example.

A MOS static RAM is used as the memory cell 13, and a flip-flop composed of four MOS transistors Q1 to Q4 is used as the memory cell.

The writing or reading is performed by the signal on the selection line W or R, respectively, into the MOS) transistor (L++ Qat or QSO).
+Qu. This is a method in which the A1 data line WDt or the read data line xtD is turned on. In addition, in the nine examples, W
Inverse signals WD and RD of D and RD are also input and output to improve the operating characteristics during writing and reading.

As explained above, the present invention is particularly advantageous by providing two sets of independent decoders for reading and writing in the data register memory. If you have no choice but to operate the cut/in/out time switch,
It is possible to drive at a speed comparable to the iway multiplicity, and it is possible to achieve an increase in the speed of one-hour switching, and there are effects such as being able to improve the manufacturing yield.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional time switch.
FIG. 2 is a block diagram showing the configuration of an embodiment of the time switch according to the present invention, FIG. 6 is a block diagram showing an example of the internal configuration of the data bus memory shown in FIG. 2, and FIG. FIG. 2 is a circuit diagram showing a configuration example of a memory cell shown in FIG. 10.10'...Data bus memory, 11...〒1
12... read address decoder. 16...Memory cell, 20...Write counter,'
50... Read control memory, 40... Multiplex circuit. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. In the data bus memory which is the time switch element of the time division switch? It is characterized by comprising two sets of address input ports corresponding to the two sets of decoders: a write address decoder that selects the A' write address, a read address decoder that selects the read address, and the write and read address decoders. and time switch.