JPS6027160A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6027160A JPS6027160A JP58134483A JP13448383A JPS6027160A JP S6027160 A JPS6027160 A JP S6027160A JP 58134483 A JP58134483 A JP 58134483A JP 13448383 A JP13448383 A JP 13448383A JP S6027160 A JPS6027160 A JP S6027160A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- internal processing
- chip
- design
- peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 230000002093 peripheral effect Effects 0.000 claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 abstract description 14
- 238000000034 method Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 235000002492 Rungia klossii Nutrition 0.000 description 1
- 244000117054 Rungia klossii Species 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ＣＭＯ８論理集積回路ケ構成する場合、こｆ
′Ｌ、’ｉ複数個のテップに分割するとともに、周辺回
路用チップとして、マスクスライス基板等の汎用性の高
いもの葡用いることにより、設計の融通性、製造歩留り
および性能向上を図った半導体装置の構成に関するもの
である。Detailed Description of the Invention (Industrial Field of Application) The present invention provides
'L,'i A semiconductor device that improves design flexibility, manufacturing yield, and performance by dividing into multiple steps and using highly versatile materials such as mask sliced substrates as chips for peripheral circuits. It is related to the configuration of.
（従来技術）
一般の半導体装置は、第１図に示すように、主機能金持
つ内部処理回路１を中央に配置し、その外周に外部接続
回路とのインフッエイスケ取るための、周辺回路２と呼
ぶ入出力回路群３を配置した１チツプ構成である。４ｑ
接続端子部全示す。そのため、外部に接続さｎる回路に
依存した回路設計となり、レイアウト後の仕様変更に対
しては、自由度がない。′！！た、一基板上で作成され
るため、実現機能、回路に適合したデバイスケ選択でき
ず、内部処理回路とも同一のデバイス音用いることとな
る。さらに、周辺回路部は、多量の電諒供給が必要であ
り、パッケージ全音めた総合的放熱処理、特にＣＭＯ８
の場合に外部ノイズからのラッチアップ、周辺Ｎ°路に
２ける大電流オン・オフにより発生する雑音等電気的特
性ケチツブ全体から考慮しなｔブればならない。貰た、
ＩＶＩ ＯＳ系の集積回路の場合には、一般に周辺の出
力回路の躯動能力が小さく、大規模なシステムに応用す
ム場合には、ＴＴＬのＭＳＩ／ＳＳＩ等駆動能力の高駆
動能力ケージヶ介して、他の回路部分に信号ケ供給する
必要が生じ、結果としてシステムの物理的サイズを大型
にしてしまう。チップ周辺部は、外部接続回路とのイン
タフェイス孕とりもつ入出力回路群３とともに、チップ
をパッケージに搭載し、パッケージのビンと全接続する
ための接続端子部４が環状に配置される。一般に入出力
回路は、大きな駆動能力を要求さｎ１接続端子部も１０
０μｍｘ １００μｍ程度の大面積が必要であるため、
内部処理回路の高密度化に対応したチップ面積の縮少が
できない。これは、製造面においても影響が犬である。(Prior Art) As shown in FIG. 1, a general semiconductor device has an internal processing circuit 1 having a main function arranged in the center, and peripheral circuits 2 arranged around its outer periphery to provide interface with external connection circuits. It has a one-chip configuration in which a group of input/output circuits 3 called . 4q
All connection terminals are shown. Therefore, the circuit design depends on externally connected circuits, and there is no flexibility in changing specifications after layout. ′! ! In addition, since it is created on one board, it is not possible to select a device that matches the realized function and circuit, and the same device sound is used for the internal processing circuit. Furthermore, the peripheral circuitry requires a large amount of power supply, and comprehensive heat dissipation treatment including the whole package is required, especially for CMO8.
In this case, latch-up from external noise, noise generated by large current on/off in the surrounding N° path, etc. must be taken into account from the overall electrical characteristics. I got it.
In the case of IVI OS-based integrated circuits, the peripheral output circuits generally have a small dynamic capacity, and when applied to a large-scale system, it is necessary to use a high drive capacity cage such as TTL MSI/SSI. , it becomes necessary to supply signals to other circuit parts, resulting in an increase in the physical size of the system. In the peripheral area of the chip, together with an input/output circuit group 3 that provides an interface with external connection circuits, a connection terminal part 4 for mounting the chip on a package and making all connections to the vias of the package is arranged in a ring. In general, input/output circuits require a large drive capacity, and the n1 connection terminal also has a
Since a large area of about 0 μm x 100 μm is required,
It is not possible to reduce the chip area to accommodate higher density internal processing circuits. This has a huge impact on the manufacturing side as well.
なぜなら、マスク作成装置、露光装置等の製造装置のテ
ツプサイズ製造限界がおること、チップサイズ拡大によ
る製造歩留りの低下金招くからである。This is because there is a tip size manufacturing limit of manufacturing equipment such as mask making equipment and exposure equipment, and the manufacturing yield is lowered due to the increase in chip size.
（発明の目的）
本発明は、こｎ、らの欠点を解決するために提案された
もので、内部回路２周辺回路のｌテップ構成から、内部
回路と周辺回路と會分割し、複数テップ構成とし、設計
の自由度全拡大させ、谷テッグ別個に製清し、組合せに
より実現することから、電気的、熱的特性を向上させる
とともに、総合的製造歩留りの向上全図ることを目的と
する。(Objective of the Invention) The present invention was proposed in order to solve these drawbacks.The present invention has been proposed to solve these drawbacks. The purpose is to completely expand the degree of freedom in design, manufacture the Tani Tegs separately, and realize them by combining them, thereby improving electrical and thermal characteristics as well as improving the overall manufacturing yield.
（発明の構成）
上記の目的を達成するため、本発明はＣＭＯ８論理集積
回路を、主機能葡持つ内部処理回路と、外部接続回路と
のインタフェイスを取るための周辺回路とに分割し、こ
れら盆複数個の半導体チップにエリ構成し、１つの半導
体パッケージに搭載することを特徴とする半導体装置ケ
発明の装置とするものである。(Structure of the Invention) In order to achieve the above object, the present invention divides a CMO8 logic integrated circuit into an internal processing circuit having a main function and a peripheral circuit for interfacing with an external connection circuit. A semiconductor device according to the invention is characterized in that a plurality of semiconductor chips are arranged in a tray and mounted in one semiconductor package.
次に本発明の実施例ヶ添付図面について説明する。なお
実施例は一つの例示であって、本発明の精神上逸脱しな
い範囲で、種々の変更あるいは改良を行いうろことは言
うまでもない。Next, an embodiment of the present invention will be explained with reference to the accompanying drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.
第２図は本発明の実施例を示すもので、内部処理回路チ
ップと周辺回路チップとに分割し、これらのテッグ會１
つのパッケージ上に搭載した例奮示す。搭載後１．相互
にチップ間ケ接続する。図において、５は主機能ケ持つ
内部処理１四路テツグ、６は周辺回路チップでちる。全
回路會この様な複数ナツプ分割の構成とすることにより
、内部処理回路チップ５および周辺回路チップ６におい
て実現する回路に適合したデバイスを使用できる。さら
に、周辺回路テップ６にマスタスライス等の汎用性の高
いチップを用いることによ勺、特性づけら扛ていない周
辺回路チップをあらかじめ大量に準備しておくことが可
能であり、外部仕様の変更に対し、一部のマスクの修正
により対処できる。周辺回路構成によっては、各チップ
全パッケージ搭載後、配線接続経路の選択によυ対処す
ることも可能である。また、内部処理回路と周辺回路が
別チップに分離されているため、０ＭＯ８の場合、ラッ
チアップ等全引越す外部からの影響を周辺回路チップで
処理でき、また、周辺回路における大電流オン・オフに
より発生する雑音から内部処理回路の誤動作全防止でき
る。放熱処理に対しては、大量の電力を消費する周辺回
路から発生する熱が基板を介して直接伝導することなく
各テップの発熱量に従ってテッグ設計、実装方式をとる
ことができる。チップサイズも内部処理回路のチップ寸
法が周辺回路チップの寸法に左右さｎず、高集積化の効
果が発揮さｎ、Ｏ）能な限９の縮少ができる。したがっ
て、チップ製造が容易となるとともに、チップの選択１
組合せによシ全回路全実現するための、個々のチップ製
造歩留りを向上させるとともに、総合的な歩留り全向上
させることができる。また、周辺回路用チップにバイポ
ーラ系デバイスケ用いｎば、他の回路部分への信号供給
時の駆動能力を高くでき、駆動能力全補助する別パッケ
ージが不要となるため、全体としてシステムを小型化で
きる。さらに、アナログインタフニースケ持つアナログ
・ディジタル混載型のＬＳＩの場合にも１、ｊ、。FIG. 2 shows an embodiment of the present invention, which is divided into an internal processing circuit chip and a peripheral circuit chip.
We will show you an example of how it is mounted on one package. After installation 1. Connect the chips to each other. In the figure, 5 is an internal processing chip having main functions, and 6 is a peripheral circuit chip. By configuring the entire circuitry to be divided into multiple naps, devices suitable for the circuits realized in the internal processing circuit chip 5 and the peripheral circuit chip 6 can be used. Furthermore, by using a highly versatile chip such as a master slice for the peripheral circuit step 6, it is possible to prepare a large amount of uncharacterized peripheral circuit chips in advance, making it possible to change external specifications. However, this can be addressed by modifying some masks. Depending on the peripheral circuit configuration, it is also possible to deal with υ by selecting the wiring connection route after each chip is fully packaged. In addition, since the internal processing circuit and peripheral circuit are separated into separate chips, in the case of 0MO8, all external influences such as latch-up can be handled by the peripheral circuit chip, and large current on/off in the peripheral circuit can be handled by the peripheral circuit chip. Malfunctions of internal processing circuits can be completely prevented from generated noise. For heat dissipation processing, the heat generated from peripheral circuits that consume a large amount of power is not directly conducted through the board, and the TEG design and mounting method can be adopted according to the amount of heat generated by each step. As for the chip size, the chip size of the internal processing circuit does not depend on the size of the peripheral circuit chip, and the effect of high integration can be achieved. Therefore, chip manufacturing becomes easy, and chip selection 1
By combining the two, it is possible to improve the manufacturing yield of each individual chip for realizing the entire circuit, and also to improve the overall yield. In addition, by using bipolar devices for peripheral circuit chips, the drive capacity when supplying signals to other circuit parts can be increased, and a separate package that supports all drive capacity is not required, so the overall system can be made smaller. . Furthermore, in the case of an analog/digital mixed type LSI with an analog interface, 1,j,.
例えば、インタフェース部のアナログ・アナログ変換回
路ないしは、ディジタル・アナログ変換回路と内部のデ
ィジクル回路を別チップ（を成とし、個々に最適プロセ
ス、最適設計が行え、性能向上と低価格化を達成できる
。For example, the analog-to-analog converter circuit or digital-to-analog converter circuit in the interface section and the internal digital circuit can be formed on separate chips, and the optimum process and design can be performed individually, thereby improving performance and reducing costs.
（発明の効果）
紙上のように、本発明によれば全回路全主機能全持つ内
部処理回路と、外部接続回路とのインタフェイスを取る
ための周辺回路に分割し、これ全複数チップで実現する
ことにより、従来の１チツプ構成に対して、回路設計、
バタン設計において柔軟性が高く、製造歩留りが向上す
ることにニジ生産コスＩｆ低下させることができる。ま
た、電気的、熱的特性の改善が図れ、ＣＭＯ３論理集積
回路の大規模化、多端子化のなかで、パッケージ設計に
有効である等の効果を有する。(Effects of the Invention) As described on paper, according to the present invention, all circuits are divided into an internal processing circuit that has all main functions and a peripheral circuit for interfacing with external connection circuits, and all of these are realized using multiple chips. By doing this, compared to the conventional one-chip configuration, circuit design,
The baton design has high flexibility, improves manufacturing yield, and can reduce production costs If. In addition, electrical and thermal characteristics can be improved, and as CMO3 logic integrated circuits become larger and have more terminals, it is effective in package design.
第１図は従来のテップレイアウト構成、第２図は本発明
における主機能を持つ内部処理回路と周辺Ｎ路との分割
による構成の例を示す。
１・・・・・・・・・内部処理回路
２・・・・・・・・・周辺回路
３・・・・・・・・−人出力回路群
４・・・・・・・・・接続端子部
５・・・−・・・・・内部処理回路チップ６・・・・・
・・・・周辺回路チップ
特許出願人 日本電信電話公社FIG. 1 shows an example of a conventional step layout configuration, and FIG. 2 shows an example of a configuration in which an internal processing circuit having a main function and a peripheral N path are divided according to the present invention. 1...Internal processing circuit 2...Peripheral circuit 3...-Human output circuit group 4...Connection Terminal section 5 --- Internal processing circuit chip 6 ---
...Peripheral circuit chip patent applicant Nippon Telegraph and Telephone Public Corporation
Claims (1)
、外部接続回路とのインタフェイス全敗るための周辺回
路とに分割し、これらを複数個の半導体チップにより構
成し、１つの半導体パッケージに搭載すること全特徴と
する半導体装置。A CMO8 logic integrated circuit is divided into an internal processing circuit that has the main function and a peripheral circuit that completely fails to interface with external connection circuits, and these are constructed from multiple semiconductor chips and mounted in one semiconductor package. A semiconductor device with all the characteristics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58134483A JPS6027160A (en) | 1983-07-25 | 1983-07-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58134483A JPS6027160A (en) | 1983-07-25 | 1983-07-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6027160A true JPS6027160A (en) | 1985-02-12 |
Family
ID=15129379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58134483A Pending JPS6027160A (en) | 1983-07-25 | 1983-07-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6027160A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5997212A (en) * | 1996-09-30 | 1999-12-07 | Hinode, Ltd. | Cover for underground structures, body thereof and frame therefor |
| US6000878A (en) * | 1996-07-29 | 1999-12-14 | Hinode, Ltd. | Cover for underground structures |
| WO2022019522A1 (en) * | 2020-07-24 | 2022-01-27 | 한양대학교 산학협력단 | Three-dimensional flash memory having improved integration density |
| KR20220026246A (en) * | 2020-08-25 | 2022-03-04 | 한양대학교 산학협력단 | Three dimensional flash memor with structure for efficient layout |
| US11515333B2 (en) | 2019-03-29 | 2022-11-29 | Iucf-Hyu (Industry-University Cooperation Foundation Hanyang University) | Ferroelectric material-based three-dimensional flash memory, and manufacture thereof |
-
1983
- 1983-07-25 JP JP58134483A patent/JPS6027160A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6000878A (en) * | 1996-07-29 | 1999-12-14 | Hinode, Ltd. | Cover for underground structures |
| US5997212A (en) * | 1996-09-30 | 1999-12-07 | Hinode, Ltd. | Cover for underground structures, body thereof and frame therefor |
| US11515333B2 (en) | 2019-03-29 | 2022-11-29 | Iucf-Hyu (Industry-University Cooperation Foundation Hanyang University) | Ferroelectric material-based three-dimensional flash memory, and manufacture thereof |
| WO2022019522A1 (en) * | 2020-07-24 | 2022-01-27 | 한양대학교 산학협력단 | Three-dimensional flash memory having improved integration density |
| KR20220026246A (en) * | 2020-08-25 | 2022-03-04 | 한양대학교 산학협력단 | Three dimensional flash memor with structure for efficient layout |
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