JPS60261075A - Time axis correcting device of digital reproducing signal - Google Patents

Abstract

PURPOSE:To attain an analog signal with high quality without distortion by writing a digital signal during reproduction into a memory, using a clock signal without time base fluctuation to read the digital signal thereby restoring a reproducing signal. CONSTITUTION:A reproduced pseudo video signal (b) including time base variation reproduced from a VTR1 is fed to a data read circuit 10 in a time axis correcting device 5 and a synchronizing signal separator circuit 11. The separated composite synchronizing signal is fed to an oscillation circuit 12 and a read control circuit 13, and only a digital signal in the signal (b) is written in a memory 14. A composite synchronizing signal (c) without time base variation is fed to the oscillation circuit 15 from a PCM audio processor 2 and a clock signal is fed to a read control circuit 16 and a video signal generating circuit 17. Thus, the memory 14 is read by a clock signal without time base variance and a reproducing signal without time base variance is restored by a mixer 18. Thus, the analog signal obtained by the processor 2 is formed into a high quality signal without distortion.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a time axis correction device for a digital reproduction signal.
The present invention relates to a time axis correction device for a digital reproduction signal that performs time axis correction of a reproduction signal including time axis fluctuations reproduced from a recording medium.

2. Description of the Related Art Conventionally, a reproducing device reproduces a digital signal obtained by A/D converting an analog signal from a recording medium on which the digital signal is recorded, and extracts the original analog signal by D/A converting the digital signal. There is. Disks, magnetic tapes, etc. are used as recording media for recording the above-mentioned digital signals. Therefore, it is inevitable that the digital signal reproduced due to variations in the rotation of the disk and variations in the running of the tape during reproduction will be a signal that includes variations in the time axis.

FIG. 3 shows a block diagram of an example of a conventional digital signal reproducing device. In the figure, reference numeral 1 denotes a rotary head type video tape recorder, which reproduces and outputs pseudo video signals recorded on tracks inclined in the longitudinal direction of a magnetic tape. This pseudo video signal is, for example, NRZ modulated P
'This is a signal in which a digital signal such as a CM signal is superimposed on a standard television system composite synchronization signal. The reproduced pseudo video signal is supplied to the PCM audio processor 2, where each bit of the NRZ modulated PCM signal is extracted and NRZ demodulated. The P obtained by this
The CM signals are sequentially written into the memory, subjected to processing such as dinterleaving, and sequentially read out using a stable clock signal generated within the processor 2 with no time axis fluctuation.

The PCM signal thus obtained is subjected to error correction, etc., and then A/A converted to an analog signal. If this analog signal is an audio signal, it is supplied to the speaker 3 for sound generation. The PCM audio processor 2 also supplies a composite synchronization signal to the video tape recorder 1 to cause it to operate in synchronization.

Problems to be Solved by the Invention In the above conventional device, the memory in the processor 2
It absorbs time axis fluctuations contained in signals reproduced from magnetic tape. However, the time axis fluctuation of the pseudo video signal supplied to the processor 2 affects the operation of the arithmetic unit that performs various processes of the processor 2, and the power supply of the processor 2,
This changes the ground potential, etc., and even affects the clock signal and PCM signal supplied to the D/A converter.

Therefore, there was a problem in that the analog signal output from the processor 2 was distorted.

Therefore, the present invention solves the above problems by writing the digital signal in the reproduced signal into a memory, reading out this digital signal using a clock signal with no time axis fluctuation, and restoring the reproduced signal. The purpose of the present invention is to provide a time axis correction device.

Means and operation for solving the problems The present invention generates a first clock signal synchronized with a reproduced signal including time axis fluctuations reproduced from a recording medium, and
a signal reading means for reading a digital signal in a reproduced signal using a clock signal; a memory for sequentially writing the read digital signals; and a signal reading means for generating a stable second clock signal without time axis fluctuation; The apparatus is constructed of a signal restoring means for sequentially reading out digital signals from the memory using the signals and restoring a reproduced signal without time axis fluctuations. An embodiment thereof will be described with reference to FIG. 1 and subsequent figures.

Embodiment FIG. 1 shows a block system diagram of an embodiment of a digital signal reproducing device to which the device of the present invention is applied. In the figure, the same parts as in FIG. 3 are given the same reference numerals. In FIG. 1, reference numeral 1 denotes a rotary head type video cheap reloader, which reproduces and outputs pseudo video signals recorded on tracks inclined in the longitudinal direction of a magnetic tape. This pseudo video signal is the second
As shown in the figures (Δ) and (B), a digital signal such as an NRZ-modulated PCM signal is superimposed on a standard television system composite synchronization signal. The digital signal follows the equivalent pulse of one field's worth of composite synchronization signal <2
For example, a 128-bit digital signal a to which a synchronization bit has been added is superimposed on each horizontal scanning period. The above video tape recorder 1 is a PC which will be described later.
Although it is operated in synchronization with the composite synchronization signal C from the M audio processor 2, the reproduced pseudo video signal includes time axis fluctuations due to fluctuations in the running speed of the magnetic tape, etc.

This reproduced pseudo video signal is supplied to a data reading circuit 10 and a synchronization signal separation circuit 11 in the time axis correction device 5.

Here, the time axis correction device 5 is connected to the video tape recorder 1.
It is separate from each of the PCM audio processors 2, which will be described later, and has an independent power supply and ground. The synchronization signal separation circuit 11 separates and generates a composite synchronization signal from the reproduced pseudo video signal and supplies it to the oscillation circuit 12 and the reading control circuit 13. The oscillation circuit 12 is composed of a horizontal synchronization signal separation circuit and a phase-locked loop (PLL), and is separated from the above-mentioned reproduced pseudo video signal and generates a horizontal synchronization signal of a composite synchronization signal that itself includes time axis fluctuations. A first clock signal having a repetition frequency of 12 MHz, for example, is generated in synchronization with the horizontal synchronizing signal, and this clock signal is supplied to the read control circuit 13.

The reading control circuit 13 divides the frequency of the clock signal during the existence period of the digital signal a of the reproduced pseudo video signal as shown in FIGS. 2(A) and 2(B) with reference to the vertical and horizontal synchronizing signals of the composite synchronizing signal. For example, a repetition frequency of 3MH obtained by
A latch pulse of z is generated and supplied to the data reading circuit 10. At the same time, a write permission signal obtained by inverting the latch pulse and an address signal obtained by counting the latch pulse are supplied to the memory 14. As a result, the data reading circuit 10 latches only the digital signal a in the reproduced pseudo video signal and supplies it to the memory 14, and the digital signals are sequentially written into the memory 14. The data reading circuit 10. Synchronous signal separation circuit 119 oscillation circuit 12. The reading control circuit 13 constitutes a signal reading means.

The oscillation circuit 15 includes a horizontal synchronization signal separation circuit, a frame synchronization signal separation circuit, and a phase locked loop (PLL).
The PCM audio processor 2 supplies the composite synchronization signal C shown in FIG. The second pulse has a stable repetition frequency of 12 MHz, which is synchronized with the synchronization signal and has no time axis fluctuation.
A clock signal is generated and supplied to the successive control circuit 16. Further, this second clock signal is frequency-divided to obtain a pulse signal with a repetition frequency of 3M1-1z, and this pulse signal and a frame synchronization signal separated and generated from the composite synchronization signal C are supplied to the video signal generation circuit 17.

The video signal generation circuit 17 is supplied with the above-mentioned pulse signal with a repetition frequency of 3MH2 and the frame synchronization signal, and is delayed from the composite synchronization signal C by a time nH (n is a natural number, -1 is one horizontal scanning period), A stable composite synchronization signal d with no time axis fluctuation is generated and supplied to the successive control circuit 16 and the mixer 18. Note that the above-mentioned time nH is set to a value that is sufficiently larger than the time axis fluctuation α with respect to the composite synchronization signal C of the reproduced pseudo video signal outputted from the video tape recorder 1. In this connection, memory 14 stores time n1-
It has sufficient storage content to store the digital signals read within 1.

The readout control circuit 16 uses the vertical and horizontal synchronization signals of the composite synchronization signal d as a reference and divides the pulse signal from the oscillation circuit 15 to determine the existence timing of the digital signal in FIGS. 2(A) and (B). Composite synchronization signal d at similar timing
An address signal and a successive permission signal for reading out digital data to be superimposed on the memory 14 from the memory 14 are generated and supplied to the memory 14. As a result, the digital signal a is read out from the memory 14 in the same order as in writing and is supplied to the mixer 18. The mixer 18 superimposes the digital signal a on the composite synchronization signal d, thereby obtaining a stable pseudo video signal e without time axis fluctuations shown in FIG.
The signal is supplied to the audio processor 2. Above oscillation circuit 1
5. Read control circuit 16. Video signal generation circuit 17. The mixer 18 constitutes signal restoration means.

The PCM audio processor 2 supplies a composite synchronization signal C obtained by separating it from the pseudo video signal e to the video cheap reloader 1 and the time axis correction device 5. Further, the digital signal a is dispersed from the pseudo video signal e and NRZ demodulation is performed. The PCM signals obtained thereby are sequentially written into a memory, subjected to processing such as gain interleaving, and sequentially read out using a stable clock signal with no time axis fluctuation. The PCM signal thus obtained is subjected to processing such as error correction, and then D/A converted to an analog audio signal, which is supplied to the speaker 3 for sound generation.

The pseudo video signal e from which time axis fluctuations have been removed in this way is P
Since the signal is supplied to the CM audio processor 2, the arithmetic units in the processor 2 that perform various processes are not affected by fluctuations in the time axis, and the power supply, ground potential, etc. of the processor 2 do not fluctuate. Therefore, the clock signal and PCM signal in the D/A converter become stable, and the obtained analog signal becomes distortion-free.

The device of the present invention is not limited to a device for reproducing audio PCM signals using a video tape recorder, but can also be applied to a digital signal reproducing device using a fixed head digital tape recorder, a digital audio disc reproducing device, etc. , but is not limited to the above embodiments.

Effects of the Invention As described above, the time axis correction device for digital reproduced signals according to the present invention generates a first clock signal synchronized with a reproduced signal including time axis fluctuations reproduced from a recording medium, and A signal reading means for reading a digital signal in a reproduced signal using a clock signal, a memory for sequentially writing the read digital signal, and a second clock signal for generating a stable second clock signal without time axis fluctuation; The processing circuit that is supplied with the reproduced signal from the signal restoration means and outputs an analog signal is configured with a signal restoring means that sequentially reads digital signals from the memory using It is not affected by axis fluctuations, there is no fluctuation in the power supply or ground potential of this processing circuit, the clock signal and digital signal in the D/A converter are stable, and the resulting analog signal is high quality without distortion. It has the following features:

[Brief explanation of the drawing]

Fig. 1 is a block system diagram of an embodiment of a digital signal reproducing device to which the device of the present invention is applied, Fig. 2 is a signal waveform diagram of each part of the device shown in Fig. 1, and Fig. 3 is an example of a conventional digital signal reproducing device. FIG. DESCRIPTION OF SYMBOLS 1... Video tape recorder, 2... PCM audio processor, 5... Time axis correction device, 10...
Data reading circuit, 11... Synchronization signal separation circuit, 12° 15... Oscillation circuit, 13... Reading control circuit, 14.
. . . Memory, 16 . . . Readout control circuit, 17 . . . Video signal generation circuit, 18 . . . Mixer. Figure 2 For Tsubaki → Procedural amendment April 9, 1985 Manabu Shiga, Commissioner of the Patent Office (Examiner of the Patent Office) 1. Indication of the case 1982 Patent Application No. 117357 2. Title of the invention Digital Patent for time axis correction device 3 for reproduced signals, person who makes corrections Applicant address Kumo 221 3-12 Moriya-cho, Kanayō-ku, Yokohama-shi, Kanagawa Prefecture Name (432) Victor Japan Co., Ltd. Representative Director and President Michi Shishi - Department 4. Agent 5. Date of amendment order. Voluntary amendment 6. Detailed description of the invention in the specification to be amended. 7. Contents of amendment (1) In the specification, [Storage content J in the first line of page 9 is corrected to read "storage capacity." ■ Delete "pseudo...obtained" from lines 18 to 19 on page 9.

Claims (1)

[Claims] a signal reading means for generating a first clock signal synchronized with a reproduced signal including time axis fluctuations reproduced from a recording medium, and reading a digital signal in the reproduced signal using the first clock signal; A memory into which the digital signals are sequentially written, a stable second clock signal with no time axis fluctuations, and a memory which sequentially reads the digital signals from the memory using the second clock signal, and a memory with no time axis fluctuations. A time axis correction device for a digital reproduction signal, comprising a signal restoration means for restoring the reproduction signal.