JPS63272190A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To perform drop-out compensation, time base variance correction, or the like by reading out a digital signal from a memory in synchronism with a reference clock signal having a certain cycle and reading out the digital signal stored in the memory during the drop-out period to substitute dropped-out data with this signal. CONSTITUTION:A clock signal corresponding to the variance of the time base included in an analog signal is generated from the analog signal read from a recording medium, and the analog signal is converted to a digital signal in synchronism with this clock signal and this digital signal is stored in a memory 23 in synchronism with the clock signal. A detecting means 30 which detects the occurrence of drop-out in the analog signal is provided, and the digital signal is read out from the memory 23 in synchronism with the reference clock signal having a certain cycle, and the digital signal stored in the memory 23 is read out during the drop-out period in accordance with the detection output of the detecting means 30 and dropped-out data is substituted with this signal. Thus, the same memory is used to perform drop-out compensation, time base variance correction, or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a digital signal processing circuit suitable for use in an image reproduction device such as a video disc player or a video tape recorder.

(Prior Art) As is well known, recent image playback devices such as video disk players and video tape recorders convert television signals read from disks or tapes into digitized data. Digital image processing techniques have been introduced that allow various special image processing to be performed by writing and reading image signals into and from memory.

FIG. 2 shows a conventional signal processing means used in a video disc player incorporating such digital image processing technology. That is, reference numeral 11 in the figure is an input terminal to which an RF multiplied signal obtained by reproducing a disk (not shown) is supplied. The RF multiplied signal fed to this input terminal 11 (j%) is demodulated into an analog television signal by an FM demodulation circuit 12.

Then, the digital television signal outputted from the FM demodulation circuit 12 is compensated for the missing portion due to dropout by a dropout compensation circuit 13 using a one-horizontal opening period delay method, and then processed by a delay element such as a CCD. The signal is supplied to the built-in time axis fluctuation correction circuit 14, and jitter components are removed.

In this way, the analog television signal output from the time axis variation correction circuit 14 is converted into a digital television signal by the A/D (analog/digital) conversion circuit 15 and stored in the field memory 16. The digital television signal read out from the field memory 1G is converted into an analog television signal by a D/A (digital/analog) conversion circuit 17°, and sent to an image processing system (not shown) via an output terminal 18. It is supplied and used for image display.

Here, the field memory 16 stores one field (
It has a capacity to store digital television signals for 202H), and the A/D conversion circuit 15° field memory 16 and the D/A conversion circuit 17 are controlled by the memory controller 19 to store, for example, still images. Field memory 1 for special image playback such as playback
The writing and reading of digital television signals to and from 6 is controlled.

However, with the conventional signal processing means as described above,
After FM demodulation of the RF multiplied signal, dropout compensation and time axis fluctuation correction are performed, and then A/D conversion, writing and reading from field memory 1B, D/A conversion, etc. are performed for special image reproduction. Therefore, the problem arises that the configuration is complicated and the size is increased.

(Problems to be Solved by the Invention) As described above, the conventional signal processing means provided in an image reproducing device incorporating digital image processing technology has the problem of a complicated configuration and an increase in size. are doing.

Therefore, the present invention was made in consideration of the above circumstances, and provides an extremely good digital signal that can realize dropout compensation, time axis fluctuation correction, etc. with a simple configuration, and can effectively promote miniaturization. The purpose is to provide processing circuits.

[Configuration of the Invention (Means for Solving Problems) In other words, the digital signal processing circuit according to the present invention analyzes a time axis corresponding to the time axis fluctuation included in the analog signal from an analog signal read from a recording medium. A clock signal having fluctuations is generated, an analog signal is converted into a digital signal in synchronization with the clock signal, and the digital signal is stored in a memory in synchronization with the clock signal.

It is also equipped with a detection means that detects when a dropout has occurred in the analog signal. Usually, the digital signal is read out from the memory in synchronization with a reference clock signal of a fixed period, and dropout occurs according to the detection output of the detection means. During this period, the digital signal stored in the memory is read out and replaced with the dropped data.

Then, the digital signal read from the memory is converted into an analog signal in synchronization with the reference clock signal, and is used for image display.

(Function) According to the above configuration, first, since the digital signal is read out from the memory in synchronization with the reference clock signal of a constant period, it is possible to perform time axis fluctuation correction. Further, since the digital signal stored in the memory is read out during the dropout period according to the dropout detection output and replaced with the dropped data, dropout compensation can also be performed.

That is, dropout compensation, time axis variation correction, etc. can be realized using the same memory, and the configuration can be simplified and miniaturization can be effectively promoted.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, 20 is an input terminal to which an RF multiplied signal obtained by reproducing a disk (not shown) is supplied. The RF multiplied signal supplied to this input terminal 20, F
The signal is supplied to the M demodulation circuit 21 and demodulated into an analog television signal.

The analog television signal output from the FM demodulation circuit 21 is converted into, for example, an 8-bit digital television signal by the A/D conversion circuit 22, and then
The signal is supplied to the field memory 23. This field memory 23 has a memory 82 that can store one field (262H) of a digital television signal, and stores the digital television signal based on the write address output from the memory controller 24. It is.

In this case, the analog television signal output from the FM demodulation circuit 21 is sent to the burst PLL circuit 25.
a clock signal f synchronized to its color subcarrier.
PLL has been generated. In other words, this clock signal f
PI and L have time axis fluctuations corresponding to the time axis fluctuations of the analog television signal.

The A/D conversion circuit 22 receives this clock signal f PL via the memory controller 24.
The analog television signal is sampled in synchronization with L, and an analog/digital conversion operation is performed. The memory controller 24 also receives a clock signal f.
A write address is generated based on the PLL and output to the field memory 23.

Therefore, the timing at which the digital television signal is written into the field memory 23 corresponds to the time axis fluctuation of the input analog television signal.

On the other hand, the digital television No. 1a is read from the field memory 23 into which the digital television signal has been written as described above, based on the read address output from the memory controller 24. The digital television signal read from the field memory 23 is converted into the original analog television signal by the D/A conversion circuit 26, and the output terminal 2
The signal is supplied to an image processing system (not shown) via 7, and is used for image display.

In this case, the memory controller 24 generates a read address and outputs it to the field memory 23 based on a constant cycle reference clock signal fx output from a reference signal generation circuit 28 that includes a built-in crystal oscillator or the like. ing. Further, the D/A conversion circuit 26 converts the digital television signal into an analog television signal in synchronization with this reference clock signal fX.

Therefore, the timing at which the digital television signal is read from the field memory 23 is constant regardless of the time axis variation of the input analog television signal, and the time axis variation is corrected here. In addition,
The reference clock signal fx output from the reference signal generation circuit 28 is also provided to another image processing system (not shown) via an output terminal 29.

Here, the RF multiplied signal supplied to the input terminal 20 is supplied to the dropout detection circuit 30 to detect the occurrence of dropout. This dropout detection circuit 30 detects the occurrence of dropout based on the RF multiplied signal level, and upon detection, the memory controller 2
4, the write operation to the field memory 23 is stopped, and the digital television signal from one field before, which has already been written to the field memory 23, is read out to compensate for the dropout period. . In this case, since there are an integer number (455/2) x 2H of color subcarriers in one field, that is, 262 horizontal synchronization periods, it is possible to completely reproduce color components.

Therefore, according to the configuration of the embodiment described above, since the digital television signal is read out from the field memory 23 in synchronization with the basic filter signal fx of a constant period, it is possible to perform time axis fluctuation correction, and Since the digital television signal stored in the field memory 23 is read out and replaced with dropout data during the dropout period according to the dropout detection output, dropout compensation can be performed.

That is, the same field memory 23 can be used to perform dropout compensation, time axis variation correction, etc., thereby simplifying the configuration and effectively promoting miniaturization.

Furthermore, for example, in the case of still image reproduction, this can be achieved by stopping writing new digital television signals to the field memory 23 and repeatedly reading television signals of the same field.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] Therefore, as described in detail above, according to the present invention, dropout compensation, time axis fluctuation correction, etc. can be realized with a simple configuration, and an extremely good effect that can effectively promote miniaturization is achieved. It is possible to provide a digital signal processing circuit with a high level of functionality.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital signal processing means according to the present invention, and FIG. 2 is a block diagram showing a conventional signal processing means. 11... Input terminal, 12... FM demodulation circuit, 13.
... Dropout compensation circuit, 14... Time axis fluctuation correction circuit, 15... A/D conversion circuit, 1G... Field memory, 17... D/A conversion circuit, 18... Output terminal , 19... Memory controller, 20... Input terminal, 21... FM demodulation circuit, 22... A/D conversion circuit, 23... Field memory, 24... Memory controller, 25...・Burst PLL circuit, 2B
...D/A conversion circuit, 27...output terminal, 28...
・Reference signal generation circuit, 29...output terminal, 30...
Dropout detection circuit.

Claims (1)

[Claims] a clock signal generating means for generating a clock signal having a time axis variation corresponding to the time axis variation included in the analog signal from an analog signal read from a recording medium; a first conversion means for converting the analog signal into a digital signal; a memory into which the digital signal output from the first conversion means is written in synchronization with the clock signal; and a dropout occurring in the analog signal. detecting means for detecting that the digital signal has been stored in the memory during the dropout period according to the detection output of the detecting means; It comprises a readout means for reading out a signal and replacing it with dropped-out data, and a second conversion means for converting the digital signal read by the readout means into an analog signal in synchronization with the reference clock signal. A digital signal processing circuit characterized by: