JP3238988B2 - Time axis error correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video tape recorder, a video disk player, etc., in which a reproduced signal contains a time axis error. The present invention relates to a time base collector for correcting the time axis error.

[0002]

2. Description of the Related Art Conventionally, as a device for performing a time axis error of an analog signal output, a device shown in FIG. 5 used in a consumer laser disk player and a device shown in FIG. (Japanese Patent Laid-Open No. 52-931)
9). When the input video signal is a playback signal of a video disc player, a time axis error occurs in the playback signal mainly due to the rotation system. The time axis error is first corrected for each horizontal cycle, and then, within one horizontal cycle. A method of correcting an error (velocity error) of the speed difference between the start and end points of the above is adopted. The first conventional apparatus shown in FIG. 5 removes only an error for each horizontal cycle, and the second conventional apparatus shown in FIG. 6 further corrects a velocity error.

As shown in FIG. 5, the first conventional apparatus is synchronized with a burst signal (f _SC ), which is a reference signal included in the leading portion of each horizontal cycle of an input video signal and including a time axis error. The write clock (W _CK ) of the integer multiple frequency
Sync separation circuit (15), AFC (16), burst separation circuit (13)
And APC (14). Also the video signal including time base error, is converted by an A / D converter (10) into a digital signal, written in the memory (11) by W _CK. next,
The data written in the memory (11) is read by a read clock (R _CK ) from a stable reference clock generator (18) and is converted into an analog video signal by a D / A converter (12). , The time axis error for each horizontal cycle is removed. 4 _X f _SC is used as the frequency of W _CK .

The second conventional device removes a time axis error for each horizontal cycle similarly to the first device, and further corrects a velocity error as described below. As shown in FIG. 6, the velocity error is corrected by receiving a phase error signal (P _ER ) output from the APC (14) for each horizontal cycle, and the velocity error generator (2) is used in the previous horizontal cycle. taking the difference between the phase difference, the interframe difference generates a velocity error signal V _ER which is linearly approximated, added to the reference clock generator (18) connected to the phase modulator output (19).

A phase modulator (19) outputs the output (CLK) of a reference clock generator (18), which is a built-in stable oscillator, to the V
The _ER, generates R _{C K} with phase modulation to cancel the velocity error. By the phase modulated R _CK, by reading data from the memory (11), to obtain a digital video signal velocity error is corrected. The digital video signal corrected for the velocity error is converted to a D / A
The signal is converted into an analog signal by the converter (12) to obtain an analog video signal in which the velocity error has been corrected.

[0006]

A first conventional device is as follows.
Although the error for each horizontal cycle is removed, but the velocity error is not corrected, there is a limit in removing the time axis error.

On the other hand, the conventional second device removes the velocity error, but there are three types of clocks W _CK , R _CK and CLK having the same frequency but different phases in the same device. (See JP-A-63-234784). Therefore, shield between each circuit, strengthen the power supply and ground wiring of the board,
Alternatively, it may be necessary to take measures such as separating power supply and ground wiring for each circuit, which is not preferable in terms of miniaturization and cost of the device.

Further, the second conventional device changes the clock sent to the memory controller (17), so that
If the device uses the clock for other purposes, such as a clock, the first device cannot be improved by adding only a velocity error correction circuit to the conventional first device. . The present invention is to clarify a time axis error correction device that solves the above problems.

[0009]

A video signal containing a time axis error is digitized by an A / D converter (10), and a write clock W is generated based on a reference signal extracted from the video signal containing a time axis error. _CK and a phase error signal _PER are generated, a video signal digitized by the write clock _WCK is written to the memory (11), and the digitized video signal stored in the memory (11) is supplied to the reference clock generator (18). ) Read from the memory (11) by the read clock _RCK ,
In a time axis error correcting device for converting an analog video signal into an analog video signal by an A converter (12), a phase modulator (4) is connected to a D / A converter.
Connected to the output (12), the modulation input terminal of the phase modulator (4), the phase error signal P _ER from the velocity error signal V
Connect the output of the velocity error generator (2) for generating _ER, corrects the time base error of the analog video signal to an analog video signal from the D / A converter (12) by the V _ER and phase modulation .

[0010]

[Action] The velocity error signal V _ER from velocity error generator (2), the phase modulator (4) is the amount of phase shift by the velocity error included in the analog video signal from the D / A converter (12) And phase-modulate the analog video signal so as to have the opposite phase. Therefore, the velocity error contained in the analog video signal output from the phase modulator (4) is greatly reduced.

[0011]

Since the time axis error correction device of the present invention performs velocity error correction, the limit of correction of the first conventional device can be eliminated.

In the time axis error correcting apparatus according to the present invention, clocks used at the same frequency but different in phase are W _CK , R
_CK may be used, and the problem of mutual interference unlike in the conventional second apparatus is unlikely to occur.

Further, most of the conventional video disk players employ the conventional first apparatus. However, in order to modify these conventional video disk players so as to correct the velocity error, a velocity apparatus is required. Error generator
(2) and phase modulator (4)
It can be easily modified without fear of causing any other problems.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. The device of the present invention, like the second conventional device, is divided into a time axis error removing unit and a velocity error correcting unit for each horizontal cycle.

In FIG. 1, the time axis error removing unit for each horizontal cycle includes an A / D converter (10), a memory (11), a memory controller (17), and a D / A converter (12). , Burst separation circuit
(13), APC (14), sync separation circuit (15), AFC (16) and reference clock generator (18). More specifically, first, a horizontal synchronizing signal included in an input video signal is separated by a sync separation circuit (15) and sent to a frequency control circuit (AFC) (16). The AFC (16) generates a signal having the same frequency as the write clock to the memory (11) based on the horizontal synchronizing signal, and converts the signal into a phase controller (AP).
C) Send to (14). The APC (14) separates f _SC from the input video signal, and controls the phase of the signal of the frequency of the write clock so as to be the same as the phase of f _SC to generate W _CK . That is, W _CK synchronized with f _SC included in the input video signal is obtained. The _WCK is applied to a memory (11) and an A / D converter (10) to convert the input video signal into an A / D converter (1).
Digitized by 0). The digital video signal is applied to a data input of a memory (11).

On the other hand, the AFC (16) sends a start signal (W _S ) synchronized with the horizontal synchronizing signal in the input video signal to the memory controller (17), and the APC (14) transmits _WCK to the memory controller (17). ). Based on the _WS and _WCK , the memory controller (17) generates a memory address (ADRS) synchronized with the input video signal and adds the memory address (ADRS) to the memory (11) to store the input video signal in the memory at each horizontal cycle. Record in (11). The recorded data is read out from the memory (11) by a stable _RCK from a reference clock generator (18) built in the apparatus, and is returned to an analog signal by a D / A converter (12), so that each horizontal cycle is used. Eliminate time axis errors. The removal of the time axis error for each horizontal cycle is the same as in the first conventional device.

The velocity error correction section includes an APC (14)
_PER output, a velocity error generator (2) arranged between the modulation inputs of the phase modulator (4), the output of the D / A converter (12) and the output of the time axis error correction device (72) It is constituted by a phase modulator (4) arranged therebetween.

The correction of the velocity error is performed as follows. As shown in FIGS. 1 and 2, receives the P _ER for each horizontal period is output from the APC (14), velocity error generator (2) is, as described later, before in the phase difference in the horizontal period taking the difference between, to produce a velocity error signal V _ER which is linearly approximated between difference is added to the modulation input of the D / a converter (88) connected to the phase modulator output (4). The velocity error signal V _ER causes the phase modulator (4) to be in the opposite phase with the same amount of phase shift due to the velocity error contained in the analog video signal from the D / A converter (12). Apply phase modulation to analog video signal. Therefore, the velocity error contained in the analog video signal output from the phase modulator (4) is greatly reduced.

The velocity error generator (2) is, as shown in FIG. 3, for each change point of each horizontal period, and to hold the P _ER of current to the sample-and-hold circuit (SH1) simultaneously, 1
To hold the horizontal period delay circuit for one horizontal period before the P _ER passed through the (1H delayer) to the sample-and-hold circuit (SH2). S
The output of H1 and SH2 is V- which is voltage input-constant current output.
The non-inverting and inverting inputs of the I amplifier 24 are respectively applied to the VI amplifier 24, and the VI amplifier 24 outputs a constant current proportional to the voltage difference between the two inputs. That is, one horizontal period before P _ER and the current P _ER
And outputs a constant current proportional to the difference. The constant current output I _O
It is added to the capacitor C _S. The C _S is reset every change point of each horizontal period by the switch SW. Therefore,
Voltage V _S across the C _S when reset by the time since t has elapsed becomes _{V S = I O x t /} C S , and the linearly changing waveform with respect to time. V
_S went through Baffua (25), is output as V _ER. Thus, the velocity error generator (2) of the present embodiment generates the sawtooth _VER in FIG.

As shown in FIG. 4, the phase modulator (4)
The analog video signal from the A-converter (12) is applied to a non-inverting input of an amplifier (42) having a gain of 2 through a 1/2 attenuator (41). Further, the analog video signal is
Through a series circuit of _zeros and an inductance L, it is applied to the cathode of a variable capacitance diode C _V , the anode of C _V being applied to the inverting input of an amplifier 42 which is grounded by a resistor R. The connection point of the C ₀ and the inductance L, via a resistor R _B, velocity error V _ER is applied. Above, the analog video signal through the 1/2 attenuator (41), whatever the phase modulation is not received by the V _ER. on the other hand,
The analog video signal passing through C ₀ passes through a series circuit of L and C _{V and} a voltage dividing circuit by a resistor R, and an amplifier
The phase of the analog video signal at the inverting input of (42) is
It becomes a function of the variable capacitance diode C _V. V _ER modulates the phase of the analog video signal by changing the capacitance of C _V by changing the reverse bias voltage (not shown) of C _V through L and R. The output of the amplifier (42) is a composite wave of the inverted and non-inverted inputs. At the output of the amplifier (42), the degree of phase modulation by V _ER is set so as to minimize the velocity error. . The time axis error correction device (1) of the present embodiment corrects the velocity error included in the analog video signal by phase-modulating the analog video signal as described above.

In the above description, the timing between the signals is not described for easy understanding. However, it is needless to say that the timing between the signals is actually adjusted by a delay device or the like. .

The description of the above embodiments is for the purpose of illustrating the present invention, and should not be construed as limiting the invention described in the claims or reducing the scope thereof. Further, the configuration of each part of the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made within the technical scope described in the claims.

[Brief description of the drawings]

FIG. 1 is a block diagram of a time axis error correction device according to the present invention.

FIG. 2 is a signal waveform at each point in FIG.

FIG. 3 is a block diagram of a velocity error generator.

FIG. 4 is a block diagram of a phase modulator.

FIG. 5 is a block diagram of a first conventional time axis error correction device.

FIG. 6 is a block diagram of a second conventional time axis error correction device.

[Explanation of symbols]

(W _CK ) Write clock (R _CK ) Read clock (P _ER ) Phase error signal (V _ER ) Velocity error (2) Velocity error generator (4) Phase modulator (10) A / D converter (11) Memory (12) D / A converter (14) APC (18) Reference clock generator (72) Output

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 H04N 9/79-9/898

Claims (1)

(57) [Claims] 1. A video signal containing a time axis error is converted to an A /
A write clock W _CK and a phase error signal _PER are generated based on a reference signal extracted from a video signal including a time axis error by being digitized by a D converter (10).
_The video signal digitized by _CK is written to the memory (11), and the digitized video signal stored in the memory (11) is read by the read clock R from the reference clock generator (18).
Read from memory (11) by _CK and D / A converter (12)
In the time axis error correction device for converting to an analog video signal, a phase modulator (4) is connected to the output of the D / A converter (12), and a modulation input terminal of the phase modulator (4) The phase error signal P
Connect the output of the velocity error generator (2) for generating a velocity error signal V _ER from _ER, by the V _ER D /
A time axis error correction device for correcting the time axis error of the analog video signal by phase-modulating the analog video signal from the A converter (12).