JPS60254696A - Electronic circuit package - Google Patents
Electronic circuit packageInfo
- Publication number
- JPS60254696A JPS60254696A JP11062084A JP11062084A JPS60254696A JP S60254696 A JPS60254696 A JP S60254696A JP 11062084 A JP11062084 A JP 11062084A JP 11062084 A JP11062084 A JP 11062084A JP S60254696 A JPS60254696 A JP S60254696A
- Authority
- JP
- Japan
- Prior art keywords
- electronic circuit
- circuit elements
- plate
- package
- circuit package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Combinations Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電子回路パッケージに関し、特に例えばメモ
リIC等のような同一または類似の接続端子配置を有す
る板状の電子回路素子の複数個を搭載した電子回路パッ
ケージに関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an electronic circuit package, and in particular to a package mounted with a plurality of plate-shaped electronic circuit elements having the same or similar connection terminal arrangement, such as memory ICs, etc. It relates to electronic circuit packages.
従来の技術
従来、この種の電子回路パッケージは、第3図に示すよ
うに、複数の板状の電子回路素子1を良熱伝導体基板3
上の同一平面内に並べて搭載し、相互配線2によって電
気信号用外部接続端子4に接続していた。2. Description of the Related Art Conventionally, this type of electronic circuit package, as shown in FIG.
They were mounted side by side in the same plane above and connected to an external connection terminal 4 for electrical signals by mutual wiring 2.
この場合、相互配線2の長さく以下相互配線長という)
による信号伝達遅延が生じることや、相互配線長の差に
よる信号伝達時間差が生じることの欠点、さら、にパッ
ケージ全体の形状が平面的で大きなものとなることの欠
点などがあった。In this case, the length of mutual wiring 2 is hereinafter referred to as mutual wiring length)
There are disadvantages such as a delay in signal transmission due to a delay in signal transmission, a difference in signal transmission time due to a difference in mutual wiring length, and a disadvantage that the overall shape of the package is planar and large.
発明が解決しようとする問題点
本発明の目的は、相互配線長および相互配線長の差を小
さくシ、さらにパッケージの大きさを小さくすることに
よシ、従来の問題点を改善した電子回路パッケージを提
供することにある。Problems to be Solved by the Invention An object of the present invention is to provide an electronic circuit package that improves the conventional problems by reducing the mutual wiring length and the difference in mutual wiring length, and further reducing the size of the package. Our goal is to provide the following.
問題点を解決するだめの手段
本発明は上述の問題点を解決するために、複数の板状の
電子回路素子を電気信号用外部接続端子を有する良熱伝
導体基板上に搭載し、相互配線した電子回路パッケージ
において、前記複数の板状の電子回路素子のうち同−又
は類似の接続端子配置を有する電子回路素子の複数個を
一定の間隔を保って重ね合わせて搭載し、相互配線した
構成を採用するものである。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention has provided a plurality of plate-shaped electronic circuit elements mounted on a good thermal conductor substrate having external connection terminals for electrical signals, and interconnecting them. In the electronic circuit package, a plurality of electronic circuit elements having the same or similar connection terminal arrangement among the plurality of plate-shaped electronic circuit elements are mounted on top of each other at a constant interval and interconnected. This will be adopted.
作用
本発明の電子回路パッケージにおいては、積層状に搭載
された複数の板状の電子回路素子の積層間隔を極力小さ
くすることによシ、相互配線長は従来よシも小さくなシ
、それに比例して他の相互配線の長さの差も小さくなる
。Function: In the electronic circuit package of the present invention, by minimizing the stacking interval of the plurality of plate-shaped electronic circuit elements mounted in a stacked manner, the mutual wiring length is smaller than before, and is proportional to that. As a result, the difference in length between other interconnections is also reduced.
特に、複数の板状の電子回路素子が、例えばメモIJI
Cのように同一または類似の接続端子配置を有するもの
であれば、各電子回路素子のほぼ同じ位置にある接続端
子間の相互配線が積層面に対して垂直となるため、相互
配線長が最小化されると共に各相互配線長の差がほとん
どなくなる。In particular, a plurality of plate-shaped electronic circuit elements, such as Memo IJI
If the connection terminal arrangement is the same or similar as in C, the mutual wiring between the connection terminals located at almost the same position on each electronic circuit element will be perpendicular to the laminated surface, so the mutual wiring length will be the minimum. As the wiring length becomes smaller, the difference in the length of each interconnection almost disappears.
実施例
次に、本発明の実施例について図面を診照して説明する
。Embodiments Next, embodiments of the present invention will be described with reference to the drawings.
本発明の第1の実施例を斜視図で示す第1図において、
本発明の電子回路パッケージは、複数の板状電子回路素
子1と、電気信号用外部接続端子4を有する良熱伝導体
基板3とからなシ、前記複数の電子回路素子1を一定の
間隔を保って積層状に重ね合わせて前記良熱伝導体基板
3に搭載し、前記電子回路素子1の接続端子5の相互間
と、最下段の接続端子と電気信号用外部接続端子4との
間を相互配線2で接続している。したがって、従来の電
子回路パッケージに比べて相互配線長が短くなシ、パッ
ケージの面積も小さくできる効果がある。In FIG. 1 showing a perspective view of a first embodiment of the present invention,
The electronic circuit package of the present invention consists of a plurality of plate-shaped electronic circuit elements 1 and a good thermal conductor substrate 3 having external connection terminals 4 for electric signals, and the plurality of electronic circuit elements 1 are arranged at regular intervals. The electronic circuit element 1 is stacked in a laminated manner and mounted on the good thermal conductor substrate 3, and the connection terminals 5 of the electronic circuit element 1 are connected between each other and between the lowest connection terminal and the external connection terminal 4 for electrical signals. They are connected by mutual wiring 2. Therefore, compared to conventional electronic circuit packages, the mutual wiring length is shorter and the area of the package can also be reduced.
第2図は本発明の第2の実施例の斜視図である。FIG. 2 is a perspective view of a second embodiment of the invention.
複数の板状の電子回路素子1が、例えばメモリICのよ
うに1部もしくは全部の接続端子5が同一または類似の
機能を有し同一配置に列べられたもので、その他の構成
は第1の実施例と同様である。A plurality of plate-shaped electronic circuit elements 1 are arranged in the same arrangement, such as in a memory IC, in which one or all of the connection terminals 5 have the same or similar functions, and the other configuration is the same as in the first example. This is similar to the embodiment.
図に示すように、各電子回路素子1の同じ位置にある同
一または類似の機能を有する、たとえばアドレスおよび
クロックなどの接続端子5の間の相互配線2は積層面に
対して垂直となり、その線長は最小となシ、文具なる相
互配線の線長もはy同じとなシ差がなくなる。したがっ
て第1の実施例同様の効果がある。As shown in the figure, the interconnections 2 between the connection terminals 5 having the same or similar functions, such as address and clock, located at the same position of each electronic circuit element 1 are perpendicular to the lamination plane, and the lines The length is the minimum, and the line length of the mutual wiring for stationery is also the same, so there is no difference. Therefore, there is an effect similar to that of the first embodiment.
なお、第1図および第2図に示した実施例においては、
良熱伝導体基板3の上に1組の積層状に重ね合わされた
複数の電子回路素子群が搭載されているが、2組以上の
複数の電子回路素子群を搭載することも可能である。In addition, in the embodiment shown in FIGS. 1 and 2,
Although one set of multiple electronic circuit element groups stacked in a laminated manner is mounted on the good thermal conductor substrate 3, it is also possible to mount two or more sets of multiple electronic circuit element groups.
また相互配線2は複数の板状の電子回路素子1の接続端
子5相互間を図のように直接接続するのでなく、板状の
電子回路素子1のそれぞれの間に接続用中継端子を有す
る良熱伝導体板状物を挿入するなどして間接的に接続し
てもかまわない。Moreover, the mutual wiring 2 does not directly connect the connection terminals 5 of the plurality of plate-shaped electronic circuit elements 1 as shown in the figure, but has a connection relay terminal between each of the plate-shaped electronic circuit elements 1. The connection may be made indirectly, such as by inserting a heat conductor plate.
さらに、良熱伝導体基板3の形状もパッケージ全体の放
熱効果を考慮して冷却に適した形状にしてもかまわない
。−
発明の詳細
な説明したように、本発明によれば、複数の板状の電子
回路素子を積層状に重ねるように並べて相互配線するこ
とによシ、相互配線長による信号伝達遅延や信号伝達遅
延時間差を従来よシも小さくでき、さらにこの種の電子
回路パッケージの大きさを従来よシも小さくできるとい
う効果がある。Furthermore, the shape of the good thermal conductor substrate 3 may be made into a shape suitable for cooling in consideration of the heat dissipation effect of the entire package. - As described in detail, according to the present invention, by arranging and mutually wiring a plurality of plate-shaped electronic circuit elements in a stacked manner, signal transmission delays and signal transmission due to mutual wiring lengths can be reduced. The delay time difference can be made smaller than before, and the size of this type of electronic circuit package can also be made smaller than before.
第1図は本発明の第1の実施例を示す斜視図、第2図は
本発明の第2の実施例を示す斜視図、第3図は従来の一
例を示す斜視図である。
1・・・・・・板状の電子回路素子、2・・・・・・相
互配線、3・・・・・・良熱伝導体基板、4・・・・・
・電気信号用外部接続端子、5・・・・・・電子回路素
子の接続端子。
テ
察 1 凹
Φ
寮2回FIG. 1 is a perspective view showing a first embodiment of the present invention, FIG. 2 is a perspective view showing a second embodiment of the invention, and FIG. 3 is a perspective view showing a conventional example. 1... Plate-shaped electronic circuit element, 2... Mutual wiring, 3... Good thermal conductor substrate, 4...
- External connection terminal for electrical signals, 5...Connection terminal for electronic circuit elements. Testing 1 concave Φ dormitory 2 times
Claims (1)
を有する良熱伝導体基板とからなシ、前記複数の板状の
電子回路素子を前記良熱伝導体基板上に搭載し、相互配
線した電子回路パッケージにおいて、前記複数の板状の
電子回路素子のうち同一または類似の接続端子配置を有
する電子回路素子の複数個を一定の間隔を保って重ね合
わせて搭載したことを特徴とする電子回路パッケージ。a plurality of plate-shaped electronic circuit elements and a good thermal conductor substrate having external connection terminals for electrical signals; the plurality of plate-shaped electronic circuit elements are mounted on the good thermal conductor substrate; In the wired electronic circuit package, a plurality of electronic circuit elements having the same or similar connection terminal arrangement among the plurality of plate-shaped electronic circuit elements are mounted on top of each other at a constant interval. electronic circuit package.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11062084A JPS60254696A (en) | 1984-05-30 | 1984-05-30 | Electronic circuit package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11062084A JPS60254696A (en) | 1984-05-30 | 1984-05-30 | Electronic circuit package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60254696A true JPS60254696A (en) | 1985-12-16 |
Family
ID=14540409
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11062084A Pending JPS60254696A (en) | 1984-05-30 | 1984-05-30 | Electronic circuit package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60254696A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62257785A (en) * | 1986-04-30 | 1987-11-10 | イビデン株式会社 | Electronic circuit package |
-
1984
- 1984-05-30 JP JP11062084A patent/JPS60254696A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62257785A (en) * | 1986-04-30 | 1987-11-10 | イビデン株式会社 | Electronic circuit package |
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