JPH06216305A - Stacked electronic part - Google Patents
Stacked electronic partInfo
- Publication number
- JPH06216305A JPH06216305A JP5021969A JP2196993A JPH06216305A JP H06216305 A JPH06216305 A JP H06216305A JP 5021969 A JP5021969 A JP 5021969A JP 2196993 A JP2196993 A JP 2196993A JP H06216305 A JPH06216305 A JP H06216305A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- leads
- semiconductor devices
- lead
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、複数のリードが延出す
る電子部品を重ね合わせて成る積層型電子部品に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated type electronic component formed by stacking electronic components having a plurality of leads extending from each other.
【０００２】[0002]
【従来の技術】一定面積の基板上に高密度で半導体装置
やチップ部品等の電子部品を実装するには、複数の電子
部品を積み重ねて接続することが考えられる。このよう
な高密度実装を行う観点から、複数の電子部品を重ね合
わせて成る積層型電子部品がある。図５は、従来の積層
型電子部品を説明する斜視図である。この積層型電子部
品１は、例えば４つの半導体装置１０ａ、１０ｂ、２０
ａ、２０ｂが重ね合わされたもので、例えばメモリから
成る半導体装置１０ａ、１０ｂ、２０ａ、２０ｂにおい
ては、共通用の各リード１２、２２がそれぞれ重ね合わ
された状態となっている。2. Description of the Related Art In order to mount electronic components such as semiconductor devices and chip components on a substrate having a constant area with high density, it is conceivable to stack and connect a plurality of electronic components. From the viewpoint of performing such high-density mounting, there is a laminated electronic component formed by stacking a plurality of electronic components. FIG. 5 is a perspective view illustrating a conventional laminated electronic component. The multilayer electronic component 1 includes, for example, four semiconductor devices 10a, 10b, 20.
In the semiconductor devices 10a, 10b, 20a, and 20b, which are composed of, for example, memories, the common leads 12 and 22 are in a stacked state.
【０００３】また、４つの半導体装置１０ａ、１０ｂ、
２０ａ、２０ｂのうちのどれと信号の入出力を行うかを
選択するための選択用のリード１２、２２が設けられて
いる。このような積層型電子部品１を製造するには、先
ず、各半導体装置１０ａ、１０ｂ、２０ａ、２０ｂをそ
れぞれ重ね合わせ、共通用のリード１２、２２をそれぞ
れ接続する。次に、選択用のリード１２、２２をそれぞ
れの半導体装置１０ａ、１０ｂ、２０ａ、２０ｂに対し
て一つづつ接続する。このようにして各半導体装置１０
ａ、１０ｂ、２０ａ、２０ｂを重ね合わせた積層型電子
部品１を製造する。Further, four semiconductor devices 10a, 10b,
Selection leads 12 and 22 for selecting which of 20a and 20b is to be used for signal input / output are provided. In order to manufacture such a multilayer electronic component 1, first, the semiconductor devices 10a, 10b, 20a, 20b are respectively overlaid and the common leads 12, 22 are respectively connected. Next, the leads 12 and 22 for selection are connected to the respective semiconductor devices 10a, 10b, 20a and 20b one by one. In this way, each semiconductor device 10
The laminated electronic component 1 in which a, 10b, 20a, and 20b are superposed is manufactured.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、このよ
うな積層型電子部品には、次のような問題がある。すな
わち、複数の半導体装置を重ね合わせる場合、それぞれ
のリードの位置を正確に合わせる必要があり、リードの
高精度な加工が要求される。このため、リードの曲がり
等が起きた場合には、隣のリードと接触したりする不都
合が生じてしまう。また、各共通用のリードを接続した
り、選択用のリードをそれぞれの半導体装置に接続する
ための細かい作業を強いられることになり、生産性向上
の妨げとなっている。However, such a laminated electronic component has the following problems. That is, when stacking a plurality of semiconductor devices, it is necessary to accurately align the positions of the leads, which requires highly accurate processing of the leads. For this reason, when the lead bends or the like, there is a problem that the lead comes into contact with the adjacent lead. Further, it is necessary to perform a detailed work for connecting the common leads or connecting the selection leads to the respective semiconductor devices, which hinders the improvement of productivity.
【０００５】特に、メモリから成る半導体装置の場合に
は、その容量の関係から４つ半導体装置を積み重ねるこ
とが多く、各半導体装置の高さに合わせて別々のリード
加工を施す必要がある。しかも、全ての半導体装置を積
み重ねることにより、全体の高さの増加を招くととも
に、各リードの接続が煩雑になってしまう。よって、本
発明は、重ね合わせが容易で、しかも簡単に製造できる
積層型電子部品を提供することを目的とする。Particularly, in the case of a semiconductor device composed of a memory, four semiconductor devices are often stacked due to their capacity, and it is necessary to perform separate lead processing according to the height of each semiconductor device. Moreover, by stacking all the semiconductor devices, the overall height is increased and the connection of the leads becomes complicated. Therefore, an object of the present invention is to provide a laminated electronic component that can be easily stacked and can be easily manufactured.
【０００６】[0006]
【課題を解決するための手段】本発明は、このような課
題を解決するために成された積層型電子部品である。す
なわち、この積層型電子部品は、略四角形のパッケージ
の相対向する２つの側辺側から外側に向けて複数のリー
ドが延出する一方の電子部品と、この一方の電子部品と
同様な位置から複数のリードが延出する他方の電子部品
とを重ね合わせたもので、一方の電子部品のリードが延
出していないパッケージの側辺側に、他方の電子部品の
リードを配置し、しかも、各リードの下端面を略同一面
上に揃えた状態で両電子部品を重ね合わせたものであ
る。SUMMARY OF THE INVENTION The present invention is a laminated electronic component that has been made to solve such a problem. That is, this laminated electronic component is composed of one electronic component in which a plurality of leads extend outward from two opposite side sides of a substantially rectangular package, and a position similar to the one electronic component. A plurality of leads are overlapped with the other electronic component, and the leads of the other electronic component are arranged on the side of the package where the leads of the one electronic component do not extend, and This is a structure in which both electronic components are superposed with the lower end surfaces of the leads aligned on substantially the same plane.
【０００７】また、一方の電子部品および他方の電子部
品のそれぞれを、リードの延出するパッケージの側辺の
長さが、リードの延出しないパッケージの側辺の長さの
２分の１以下となる２つの半導体装置から構成し、しか
も、この２つの半導体装置のリードが延出しないパッケ
ージの側辺側をそれぞれ隣接して配置したものでもあ
る。In each of the one electronic component and the other electronic component, the length of the side edge of the package in which the lead extends does not exceed one half of the length of the side edge of the package in which the lead does not extend. It is also configured such that it is composed of two semiconductor devices, and the side edges of the packages of the two semiconductor devices in which the leads do not extend are adjacent to each other.
【０００８】[0008]
【作用】一方の電子部品と他方の電子部品とを重ね合わ
せた状態で、一方の電子部品のリードが延出していない
パッケージの側辺側に、他方の電子部品のリードを配置
するため、各リードを重ね合わせて接続する必要がな
い。すなわち、一方の電子部品と他方の電子部品との位
置合わせの許容範囲を大きくすることができる。In the state where one electronic component and the other electronic component are superposed, the lead of the other electronic component is arranged on the side of the package where the lead of the one electronic component does not extend. There is no need to stack and connect leads. That is, it is possible to increase the allowable range of alignment between one electronic component and the other electronic component.
【０００９】また、一方の電子部品と他方の電子部品と
をそれぞれ２つの半導体装置から構成することにより、
１つの積層型電子部品で４つの半導体装置を備えること
になる。しかも、リードが延出するパッケージの側辺の
長さをリードが延出しないパッケージの側辺の長さの２
分の１以下にし、２つの半導体装置のリードが延出しな
いパッケージの側辺側をそれぞれ隣接して配置すれば、
２段重ねだけでこれら４つの半導体装置を組み合わせる
ことができる。Further, by constituting one electronic component and the other electronic component from two semiconductor devices, respectively,
One laminated electronic component is equipped with four semiconductor devices. In addition, the length of the side of the package in which the leads extend is less than the length of the side of the package in which the leads do not extend.
If the sides of the package where the leads of the two semiconductor devices do not extend are arranged adjacent to each other,
These four semiconductor devices can be combined only by stacking two layers.
【００１０】[0010]
【実施例】以下に、本発明の積層型電子部品の実施例を
図に基づいて説明する。図１は、本発明の積層型電子部
品を説明する斜視図である。この積層型電子部品１は、
一方の電子部品１０と他方の電子部品２０とが重ね合わ
されたものであり、各電子部品１０、２０においては、
略四角形のパッケージ１１、２１の相対向する２つの側
辺１１ａ、２１ａから外側に向けて複数のリード１２、
２２がそれぞれ延出されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the laminated electronic component of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view illustrating a laminated electronic component of the present invention. This laminated electronic component 1 is
One electronic component 10 and the other electronic component 20 are superposed, and in each electronic component 10 and 20,
A plurality of leads 12 extending outward from two opposite sides 11a and 21a of the substantially quadrangular packages 11 and 21,
22 are extended respectively.
【００１１】以下、説明を分かりやすくするために、電
子部品２０の上に電子部品１０を重ね合わせる場合を例
として説明する。電子部品２０の上に重ね合わせる電子
部品１０のリード１２は、電子部品２０のリード２２が
延出していないパッケージ２１の側辺２１ｂ側に配置さ
れている。つまり、互いにパッケージ１１、２１のリー
ド１２、２２が延出しない側辺１１ｂ、２１ｂ側に他方
のリード２２、１２がそれぞれ配置されることで、電子
部品１０のリード１２と、電子部品２０のリード２２と
の配置位置がそれぞれ９０度ずれた状態となる。これに
より、電子部品１０のリード１２と電子部品２０のリー
ド２２との位置を合わせを行うことがなくなり、電子部
品１０と電子部品２０とを容易に重ね合わせることがで
きる。In order to make the description easy to understand, a case where the electronic component 10 is overlaid on the electronic component 20 will be described below as an example. The leads 12 of the electronic component 10 to be superposed on the electronic component 20 are arranged on the side 21b side of the package 21 in which the leads 22 of the electronic component 20 do not extend. In other words, the leads 12 of the electronic component 10 and the leads of the electronic component 20 are arranged by arranging the other leads 22, 12 on the sides 11b, 21b side where the leads 12, 22 of the packages 11, 21 do not extend from each other. The arrangement positions with respect to 22 are shifted by 90 degrees. As a result, the lead 12 of the electronic component 10 and the lead 22 of the electronic component 20 are not aligned with each other, and the electronic component 10 and the electronic component 20 can be easily overlapped.
【００１２】また、電子部品２０のパッケージ２１から
延出するリード２２は、先ず下方に折り曲げられ、パッ
ケージ２１の下面よりもわずかに下の位置で略水平に曲
げられている。さらに、電子部品１０のリード１２も、
先ず下方に折り曲げられ、前述と同様に電子部品２０の
パッケージ２１の下面よりもわずかに下の位置で略水平
に曲げられている。すなわち、電子部品１０のリード１
２の下端面１２ａと電子部品２０のリード２２の下端面
１２ａとが略同一面上に揃えられた状態となっている。
これにより、積層型電子部品１を図示しない基板に搭載
する際、全てのリード１２、２２が基板上で接触できる
ことになる。The leads 22 extending from the package 21 of the electronic component 20 are first bent downward, and are bent substantially horizontally at a position slightly lower than the lower surface of the package 21. Furthermore, the leads 12 of the electronic component 10
First, it is bent downward and is bent substantially horizontally at a position slightly lower than the lower surface of the package 21 of the electronic component 20 as described above. That is, the lead 1 of the electronic component 10
The lower end surface 12a of No. 2 and the lower end surface 12a of the lead 22 of the electronic component 20 are substantially in the same plane.
As a result, when the laminated electronic component 1 is mounted on a substrate (not shown), all the leads 12 and 22 can contact each other on the substrate.
【００１３】次に、本発明の積層型電子部品１の他の例
について説明する。図２は、積層型電子部品１の他の例
を説明する斜視図（その１）である。すなわち、この積
層型電子部品１は、例えば電子部品１０が２つの半導体
装置１０ａ、１０ｂから構成されているものであり、２
つの電子部品１０ａ、１０ｂを並べた場合の平面視面積
が、電子部品２０の平面視面積とほぼ等しくなってい
る。電子部品１０を電子部品２０の上に重ね合わせる場
合には、電子部品１０を構成する２つの半導体装置１０
ａ、１０ｂのリード１２が延出しない側辺１１ｂをそれ
ぞれ隣接して配置し、この状態で電子部品２０上に重ね
合わせる。Next, another example of the laminated electronic component 1 of the present invention will be described. FIG. 2 is a perspective view (No. 1) illustrating another example of the multilayer electronic component 1. That is, in the multilayer electronic component 1, for example, the electronic component 10 is composed of two semiconductor devices 10a and 10b.
The planar view area when the two electronic components 10a and 10b are arranged is substantially equal to the planar view area of the electronic component 20. When the electronic component 10 is superposed on the electronic component 20, the two semiconductor devices 10 forming the electronic component 10 are arranged.
The side edges 11b of the leads 10a and 10b where the leads 12 do not extend are arranged adjacent to each other, and in this state, they are superposed on the electronic component 20.
【００１４】また、半導体装置１０ａ、１０ｂの各リー
ド１２は、電子部品２０のリード２２が延出しないパッ
ケージ２１の側辺２２ｂ側にそれぞれ配置されており、
しかも、リード１２の下端面１２ａとリード２２の下端
面２２ａとが略同一面上に揃えられている。このよう
に、電子部品１０を複数の半導体装置１０ａ、１０ｂか
ら構成することで、２段重ねだけで３つの機能部品（半
導体装置１０ａ、１０ｂおよび電子部品２０）の組合せ
を行うことができる。The leads 12 of the semiconductor devices 10a and 10b are arranged on the sides 22b of the package 21 where the leads 22 of the electronic component 20 do not extend,
Moreover, the lower end surface 12a of the lead 12 and the lower end surface 22a of the lead 22 are substantially flush with each other. In this way, by configuring the electronic component 10 from the plurality of semiconductor devices 10a and 10b, it is possible to combine the three functional components (semiconductor devices 10a and 10b and the electronic component 20) only by stacking in two stages.
【００１５】また、図３は、本発明の積層型電子部品１
の他の例を説明する斜視図（その２）である。この積層
型電子部品１は、電子部品１０と電子部品２０との両方
が、それぞれ２つの半導体装置１０ａ、１０ｂ、および
半導体装置２０ａ、２０ｂから構成されたものであり、
特に、メモリから成る電子部品１０、２０の場合に有効
なものである。FIG. 3 shows a laminated electronic component 1 of the present invention.
It is a perspective view (the 2) explaining other examples of. In the multilayer electronic component 1, both the electronic component 10 and the electronic component 20 are each configured by two semiconductor devices 10a and 10b and semiconductor devices 20a and 20b, respectively.
In particular, it is effective in the case of the electronic components 10 and 20 including a memory.
【００１６】すなわち、メモリの容量の関係から４つの
半導体装置１０ａ、１０ｂ、２０ａ、２０ｂで積層型電
子部品１を構成するのが最も使用頻度が高い。この各半
導体装置１０ａ、１０ｂ、２０ａ、２０ｂのパッケージ
１１、２１は、リード１２、２２の延出する側辺１１
ａ、２１ａが延出しない側辺１１ｂ、２１ｂに対して２
分の１以下となっている。つまり、平面視２：１の長方
形から成るパッケージ１１、２１であり、その短辺から
リード１２、２２が延出するものである。電子部品１０
では、このような半導体装置１０ａ、１０ｂの側辺１１
ｂ側がそれぞれ隣接して配置され、電子部品２０では、
半導体装置２０ａ、２０ｂの側辺２１ｂ側がそれぞれ隣
接して配置されている。That is, it is most frequently used to configure the laminated electronic component 1 with the four semiconductor devices 10a, 10b, 20a and 20b because of the memory capacity. The packages 11 and 21 of each of the semiconductor devices 10a, 10b, 20a, and 20b have side edges 11 from which the leads 12 and 22 extend.
2 for sides 11b and 21b where a and 21a do not extend
It is less than one-third. That is, the packages 11 and 21 are formed of a rectangle having a 2: 1 plan view, and the leads 12 and 22 extend from the short sides thereof. Electronic component 10
Then, the side edges 11 of such semiconductor devices 10a and 10b
The b sides are arranged adjacent to each other, and in the electronic component 20,
The sides 21b of the semiconductor devices 20a and 20b are arranged adjacent to each other.
【００１７】このため、電子部品１０および電子部品２
０のパッケージ１１、２１の平面視外形はほぼ正方形と
なり、それぞれ相対向する側辺１１ａ、２１ａ側から複
数のリード１２、２２が延出するものとなる。例えば、
電子部品１０を電子部品２０の上に重ね合わせた状態に
おいて、電子部品２０のリード２２が延出しない側辺２
１ｂ側に電子部品１０のリード１２が配置される。Therefore, the electronic component 10 and the electronic component 2
The packages 11 and 21 of No. 0 are substantially square in plan view, and the leads 12 and 22 extend from the sides 11 a and 21 a facing each other. For example,
In a state where the electronic component 10 is superposed on the electronic component 20, the side 2 where the leads 22 of the electronic component 20 do not extend
The lead 12 of the electronic component 10 is arranged on the 1b side.
【００１８】これにより、各半導体装置１０ａ、１０
ｂ、２０ａ、２０ｂのリード１２、２２がそれぞれ接触
することがなくなる。また、２段重ねの高さだけで４つ
の半導体装置１０ａ、１０ｂ、２０ａ、２０ｂを組み合
わせることができることになる。しかも、リード１１、
２２の加工として、電子部品１０のリード１１の加工
と、電子部品２０のリード２２の加工の２種類だけでよ
く、複雑な配線を行う必要はない。As a result, each semiconductor device 10a, 10
The leads 12 and 22 of b, 20a and 20b do not come into contact with each other. Further, the four semiconductor devices 10a, 10b, 20a, 20b can be combined only by the height of two stacked layers. Moreover, the lead 11,
There are only two types of processing of the lead 11, that is, the processing of the lead 11 of the electronic component 10 and the processing of the lead 22 of the electronic component 20, and it is not necessary to perform complicated wiring.
【００１９】また、図４の部分斜視図に示すように、電
子部品１０と電子部品２０との位置合わせにおいて、各
パッケージ１１、２１の隅部等に穴１３、２３をそれぞ
れ設け、この穴１３、２３にピン２を貫通させることで
電子部品１０と電子部品２０との横方向に対する位置ず
れを防止することができる。本発明の積層型電子部品１
では、電子部品１０と電子部品２０との位置合わせが容
易であるが、このようなピン２を用いて確実に位置合わ
せしてもよい。また、積層型電子部品１の高さよりも多
少長いピン２を用い、このピン２を図示しない基板の穴
に挿入することで、積層型電子部品１の基板に対する位
置合わせを行ってもよい。Further, as shown in the partial perspective view of FIG. 4, holes 13 and 23 are respectively provided at the corners of the packages 11 and 21 when the electronic component 10 and the electronic component 20 are aligned with each other. , 23 to prevent the electronic component 10 and the electronic component 20 from being displaced in the lateral direction. Multilayer electronic component 1 of the present invention
Then, although the electronic component 10 and the electronic component 20 can be easily aligned with each other, such a pin 2 may be used for sure alignment. Alternatively, the pin 2 may be slightly longer than the height of the multilayer electronic component 1, and the pin 2 may be inserted into a hole of a substrate (not shown) to align the multilayer electronic component 1 with the substrate.
【００２０】なお、本実施例において、電子部品１０を
電子部品２０の上に重ね合わせた場合を例として説明し
たが、本発明はこれに限定されず、電子部品２０を電子
部品１０の上に重ね合わせるようにしてもよい。また、
本発明の電子部品１０、２０としてＴＣＰ（Ｔａｐｅ
ＣａｒｒｉｅｒＰａｃｋａｇｅ）を用いれば、重ね合わ
せた際の高さをより低くできるが、ＳＯＰ（Ｓｍａｌｌ
Ｏｕｔｌｉｎｅ Ｐａｃｋａｇｅ）やＴＳＯＰ（Ｔｈ
ｉｎＳｍａｌｌ Ｏｕｔｌｉｎｅ Ｐａｃｋａｇｅ）等
を用いても可能である。In this embodiment, the case where the electronic component 10 is superposed on the electronic component 20 has been described as an example, but the present invention is not limited to this, and the electronic component 20 is placed on the electronic component 10. You may make it overlap. Also,
TCP (Tape) is used as the electronic components 10 and 20 of the present invention.
If the Carrier Package) is used, the height when superposed can be made lower, but the SOP (Small)
Outlook Package and TSOP (Th
It is also possible to use in Small Outline Package) or the like.
【００２１】[0021]
【発明の効果】以上説明したように、本発明の積層型電
子部品によれば次のような効果がある。すなわち、各電
子部品のリードの位置を合わせる必要がないため、電子
部品の重ね合わせが容易に行える。しかも、複雑なリー
ドの接続を行う必要がないとともに、２種類のリードの
加工だけで済むことから、生産性の向上を図ることがで
きる。また、各電子部品をそれぞれ２つの半導体装置か
ら構成することにより、２段重ねだけで４つの半導体装
置を組み合わせることが可能となり、従来と同様の容量
の積層型電子部品を約半分の厚さにすることが可能とな
る。As described above, the laminated electronic component of the present invention has the following effects. That is, since it is not necessary to align the lead positions of the electronic components, the electronic components can be easily stacked. In addition, since it is not necessary to connect complicated leads and only two types of leads need to be processed, productivity can be improved. In addition, by configuring each electronic component from two semiconductor devices, it is possible to combine four semiconductor devices by only stacking two layers, and a laminated electronic component with the same capacity as the conventional one can be reduced to about half the thickness. It becomes possible to do.
【図１】本発明の積層型電子部品を説明する斜視図であ
る。FIG. 1 is a perspective view illustrating a multilayer electronic component of the present invention.
【図２】本発明の積層型電子部品の他の例を説明する斜
視図（その１）である。FIG. 2 is a perspective view (No. 1) for explaining another example of the multilayer electronic component of the present invention.
【図３】本発明の積層型電子部品の他の例を説明する斜
視図（その２）である。FIG. 3 is a perspective view (No. 2) for explaining another example of the multilayer electronic component of the present invention.
【図４】電子部品の位置合わせを説明する部分斜視図で
ある。FIG. 4 is a partial perspective view illustrating alignment of electronic components.
【図５】従来の積層型電子部品を説明する斜視図であ
る。FIG. 5 is a perspective view illustrating a conventional laminated electronic component.
１ 積層型電子部品 １０、２０ 電子部品 １０ａ、１０ｂ、２０ａ、２０ｂ 半導体装置 １１、２１ パッケージ １１ａ、１１ｂ、２１ａ、２１ｂ 側辺 １２、２２ リード １２ａ、２２ａ 下端面 DESCRIPTION OF SYMBOLS 1 Multilayer electronic component 10, 20 Electronic component 10a, 10b, 20a, 20b Semiconductor device 11, 21 Package 11a, 11b, 21a, 21b Side edge 12, 22 Lead 12a, 22a Lower end surface
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 25/18 // Ｈ０５Ｋ 1/18 Ｓ 7128−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification number Office reference number FI technical display location H01L 25/18 // H05K 1/18 S 7128-4E
Claims (2)
の側辺側から外側に向けて複数のリードが延出する一方
の電子部品と、 前記一方の電子部品と同様な位置から複数のリードが延
出する他方の電子部品とを重ね合わせて成る積層型電子
部品であって、 前記一方の電子部品と前記他方の電子部品とを重ね合わ
せた状態で、前記一方の電子部品のリードが延出してい
ないパッケージの側辺側に、前記他方の電子部品のリー
ドが配置され、かつ、各リードの下端面が略同一面上に
揃えられていることを特徴とする積層型電子部品。1. An electronic component in which a plurality of leads extend outward from two opposite side sides of a substantially rectangular package, and a plurality of leads from a position similar to the one electronic component. A laminated electronic component that is formed by stacking the other electronic component that extends, wherein the lead of the one electronic component extends in a state where the one electronic component and the other electronic component are stacked. A laminated electronic component, wherein the leads of the other electronic component are arranged on the side of the package that is not open, and the lower end surfaces of the leads are aligned on substantially the same plane.
品がそれぞれ２つの半導体装置から構成されるものであ
って、 前記各半導体装置のリードが延出するパッケージの側辺
の長さが該リードの延出しないパッケージの側辺の長さ
の２分の１以下であり、 しかも、前記２つの半導体装置のリードが延出しないパ
ッケージの側辺側が、それぞれ隣接して配置されている
ことを特徴とする請求項１記載の積層型電子部品。2. The one electronic component and the other electronic component each include two semiconductor devices, and the length of the side of the package from which the leads of each of the semiconductor devices extend is the lead. Is less than or equal to one half of the length of the side of the package that does not extend, and the sides of the package where the leads of the two semiconductor devices do not extend are arranged adjacent to each other. The laminated electronic component according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5021969A JPH06216305A (en) | 1993-01-14 | 1993-01-14 | Stacked electronic part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5021969A JPH06216305A (en) | 1993-01-14 | 1993-01-14 | Stacked electronic part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06216305A true JPH06216305A (en) | 1994-08-05 |
Family
ID=12069880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5021969A Pending JPH06216305A (en) | 1993-01-14 | 1993-01-14 | Stacked electronic part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06216305A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002062588A1 (en) * | 2001-02-02 | 2002-08-15 | Hitachi, Ltd | Electronic device and method of manufacturing the same |
| US6953991B2 (en) | 2000-07-19 | 2005-10-11 | Shindo Company, Ltd. | Semiconductor device |
| JP2007109992A (en) * | 2005-10-17 | 2007-04-26 | Furukawa Electric Co Ltd:The | Cabling method of terminals of components mounted on circuit board, and circuit board structure with terminals |
| JP2016076727A (en) * | 2015-12-24 | 2016-05-12 | トヨタ自動車株式会社 | Semiconductor device |
-
1993
- 1993-01-14 JP JP5021969A patent/JPH06216305A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6953991B2 (en) | 2000-07-19 | 2005-10-11 | Shindo Company, Ltd. | Semiconductor device |
| WO2002062588A1 (en) * | 2001-02-02 | 2002-08-15 | Hitachi, Ltd | Electronic device and method of manufacturing the same |
| US7086600B2 (en) | 2001-02-02 | 2006-08-08 | Renesas Technology Corporation | Electronic device and method of manufacturing the same |
| US7322531B2 (en) | 2001-02-02 | 2008-01-29 | Hitachi Ulsi Systems Co., Ltd. | Electronic device and method of manufacturing the same |
| US7467464B2 (en) | 2001-02-02 | 2008-12-23 | Renesas Technology Corp. | Method of manufacturing a memory card |
| JP2007109992A (en) * | 2005-10-17 | 2007-04-26 | Furukawa Electric Co Ltd:The | Cabling method of terminals of components mounted on circuit board, and circuit board structure with terminals |
| JP4646229B2 (en) * | 2005-10-17 | 2011-03-09 | 古河電気工業株式会社 | Circuit board mounting terminal wiring method and circuit board structure with terminals |
| JP2016076727A (en) * | 2015-12-24 | 2016-05-12 | トヨタ自動車株式会社 | Semiconductor device |
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