JP2000332194A - Multi-chip package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-chip package for increasing the degree of freedom of arrangement and layout of each IC chip for composing the multi-chip package. SOLUTION: In a multi-chip package 10, two upper and lower IC chips are laminated in a stack. A wiring film 3 with wiring patterns 301-304 is provided on the IC chip surface of the upper IC chip out of upper and lower IC chips 2 and 1 to be connected. Electrode pads 201, 204, 206, and 207 of the upper IC chip are connected to the corresponding electrode pad of the lower IC chip via the wiring pattern of the wiring film. Other electrode pads 202, 203, 205, 208, 209, and 210 of the upper IC chip are directly connected to the electrode pad of the lower IC chip via stitches A2, A3, A5, A8, A9, and A10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip package, and more particularly, to a multi-chip package having a structure which allows easy connection even if the arrangement direction and arrangement order of electrode pads of IC chips to be connected are different. It relates to a chip package.

[0002]

2. Description of the Related Art With miniaturization of electronic devices, high-density mounting of semiconductor devices mounted on the electronic devices is required, and as one of the measures, multi-chip packages are receiving attention. Although there are various types of multi-chip package structures, a multi-chip package having a stack structure in which IC chips are stacked in multiple stages and then sealed is attracting attention in recent years.

Here, the arrangement of electrode pads of a conventional multi-chip package having a stack structure will be described with reference to FIG. FIG. 4 is an arrangement diagram of electrode pads of a lower chip and an upper chip of a conventional multi-chip package having a stack structure. As shown in FIG. 4, a lower IC chip (hereinafter, simply referred to as a lower chip) 1 has an electrode pad (hereinafter, referred to as a lower edge) arranged along one edge (lower edge in FIG. 4) of the chip surface. It comprises lower pad rows A1 to A6 (simply called pads) and pad rows A7 to A10 arranged along the other edge (upper edge in FIG. 4) of the chip surface. An upper IC chip (hereinafter, referred to as an upper chip) 2 stacked on the lower chip 1 is a chip in which the distance between pad rows is shorter than that of the lower chip 1 and the vertical dimension is shorter than that of the lower chip 1. As shown in FIG. 4, there are provided lower pad rows of pads A1 to A6 arranged along the lower edge of the chip surface, and pad rows of pads A7 to A10 arranged along the upper edge of the chip surface. I have.

In a conventional multi-chip package having a stack structure, the arrangement direction of the pads and the arrangement order of the pads of the lower chip 1 and the upper chip 2 are usually the same as shown in FIG. Only in such a case, assembling of a stack type of chips becomes easy. In other words, the arrangement of the pads of the upper chip 2 and the arrangement order of the pads, that is, the internal connection terminals are determined by the pad arrangement of the lower chip 1, so that the upper chip 2 is newly designed according to the lower chip 1. Sometimes you have to. Conversely, if they are not the same, a multi-chip package may not be able to be formed.

When the arrangement of the pads of the upper chip 2 is perpendicular to the arrangement of the pads of the lower chip 1, as shown in FIG. 5, the lower chip 1 and the lower chip 1 which are separated from each other are arranged as shown in FIG. It is necessary to connect the pads A3 to the upper chip 2 with wires, but the connection wires extend over the upper chip 2 over a long distance. FIG. 5 is a pad layout diagram of a lower chip and an upper chip which are not easily manufactured in a conventional multi-chip package having a stack structure. As a result, when sealing the chip with the mold resin, the connection wire may be cut by the flow pressure of the resin. Further, when connecting A4 between the lower chip 1 and the upper chip 2 and connecting A5 with each other, the wires connecting them may cross each other to cause a short circuit.

In such a case, it is necessary to change the shape of the stitch and provide a stitch in which the pads of the upper chip 2 are extended in the pad arrangement direction of the lower chip 1. However, in this case, the package size becomes large due to the newly provided stitches, so that the package cannot be mounted on a system or the like, or a new board needs to be designed.

As shown in FIG. 6, when the pad arrangement is clearly different between the lower chip 1 and the upper chip 2, a conventional multi-chip package having a stack structure cannot be assembled as a multi-chip package. . FIG. 6 is another pad layout diagram of a lower chip and an upper chip which are not easily manufactured in a conventional multi-chip package having a stack structure.

[0008]

As can be seen from the above description, in order to form a multi-chip package having a stacked structure, the following restrictions have conventionally been imposed on the arrangement of pads of an IC chip for structural reasons. Was. First, the arrangement directions of the pads of the upper and lower chips need to be parallel to each other. Second, the pads corresponding to the upper and lower chips must be arranged at substantially the same intervals in the same arrangement order.

Moreover, in addition to the above restrictions, each IC chip constituting the multi-chip package may be used as a single package product other than the multi-chip package. Therefore, when matching with the pin assignment of the single package, when configuring the multi-chip package, the arrangement and arrangement order of the pads may be different between the chips, so that the existing chips or the new chip and the existing chip may be different. May be difficult to combine.

As described above, the conventional stack-structured multi-chip package has a problem that the combinations of mountable chips are limited. By the way, it is conceivable to change the pad position with an aluminum master slice corresponding to various combinations of chips.
Since redesign corresponding to the combination is required, and correction of the mask pattern is required, the number of verification steps increases. Furthermore, it is necessary to newly create a reticle required for correcting the mask pattern, which results in a large cost. On the other hand, the market demands a wide variety of combinations of memories, but the degree of freedom in pad arrangement of IC chips when forming a stacked multi-chip package is limited as described above. Under the current circumstances, it has been difficult to meet customer requirements.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-chip package having a structure in which the degree of freedom in the arrangement and arrangement of pads of each IC chip constituting the multi-chip package is increased.

[0012]

In order to achieve the above object, a multi-chip package according to the present invention is a multi-chip package in which a plurality of IC chips are stacked in a stack structure. Is provided on the IC chip surface of the upper IC chip of the upper and lower IC chips to be interconnected among the plurality of IC chips, and at least a part of the electrode pads of the upper IC chip is It is characterized in that it is connected to the corresponding electrode pad of the lower IC chip via the wiring pattern of the wiring film.

In the present invention, there is no restriction on the number of IC chips to be stacked in the stack structure. A wiring film having a wiring pattern is attached to the chip surface of the upper IC chip. It is not necessary that all of the electrode pads of the upper IC chip be connected to the electrode pads of the lower IC chip via the wiring pattern of the wiring film, and it is sufficient that at least a part of the electrode pads is connected.

In a preferred embodiment of the present invention, a stitch connected to the electrode pad of the lower IC chip is provided on the multi-chip package, and the electrode pad of the upper IC chip is connected via the wiring pattern and the stitch of the wiring film. To the corresponding electrode pads of the lower IC chip. Further, the wiring pattern has pads for wire bonding with the electrode pads at both ends.

The present invention can be applied without limitation to the arrangement direction and arrangement order of the electrode pads of the upper IC chip and the lower IC chip. In particular, the electrode pads of the upper IC chip are different from the arrangement direction of the electrode pads of the lower IC chip. It can be suitably applied to a case where the arrangement order of the electrode pads to be connected and to be connected is different between the upper IC chip and the lower IC chip, and the arrangement direction of the electrode pads of the upper IC chip Is preferably in a direction orthogonal to the arrangement direction of the electrode pads of the lower IC chip, and more preferably, when the arrangement order of the electrode pads to be connected is different between the upper IC chip and the lower IC chip. Applicable.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on embodiments with reference to the accompanying drawings. Embodiment 1 This embodiment is an example of an embodiment of a multi-chip package according to the present invention. FIG. 1 is a perspective view showing a configuration of a multi-chip package of this embodiment, and FIG. It is a perspective view explaining the method of manufacturing the example multi-chip package. The multi-chip package 10 of the present embodiment is an example in which the pad arrangement of the upper chip 2 is arranged in the same direction as the pad arrangement of the lower chip 1, that is, in parallel, but the arrangement order of the corresponding pads is different. As shown in FIG. 1, a lower IC chip (hereinafter simply referred to as a lower chip) 1 and a lower chip 1
An upper IC chip (hereinafter, simply referred to as an upper chip) 2 mounted thereon and a metal wiring film 3 attached to the upper surface of the upper chip 2. The pin assignment of the multi-chip package 10 corresponds to the basic pad arrangement of the lower chip 1.

The lower chip 1 has a pad row of pads 101 to 106 spaced apart from one edge of the chip surface and a pad row of pads 107 to 110 spaced apart from the other edge. Is provided. The upper chip 2 includes pads 202, 2 which are spaced apart from one edge of the chip surface.
03, 201 and 205, and pads 204, 206, 208 and 20 spaced apart from each other on the other edge.
7, 209, and 210 pad rows. Also,
The multi-chip package 10 includes pads 101 to 11
0 has stitches A1 to A10. The metal wiring film 3 has metal wirings 301, 302, 303, and 304.

In this embodiment, the pad 2 of the upper chip
01 corresponds to the pad 101 of the basic lower chip 1 via the package stitch A1. For that purpose, the pad 201 of the upper chip is connected to the wiring 301 of the metal wiring film 3 by the wire B102, and the wiring 301 is connected to the stitch A1 by the wire B101, and is connected to the pad 101 of the lower chip via the stitch A1. are doing. The pads 202, 203, and 205 of the upper chip are provided with the package stitches A2, A3, respectively.
And the pads 102, 1 of the basic lower chip 1 via A5
03 and 105. Pad 204 of upper chip
Correspond to the pads 104 at the opposing edges of the basic lower chip 1 via the stitches A4. Therefore, the pad 204 of the upper chip is connected to the wiring 302 of the metal wiring film 3 by the wire B402,
02 is connected to the stitch A4 by the wire B401, and is connected to the pad 104 of the lower chip via the stitch A4.

When the pad 206 of the upper chip is a stitch A
6, the pad 1 at the opposite edge of the basic lower chip 1
06. Therefore, the pad 20 of the upper chip
6 is connected to a wire 303 of the metal wiring film 3 by a wire B602, and furthermore, the wire 303 is connected to a stitch A6 by a wire B601.
Through the pad 106 of the lower chip. The pad 207 of the upper chip corresponds to the pad 107 of the basic lower chip 1 via the stitch A7. for that reason,
The pad 207 of the upper chip is connected to the wiring 304 of the metal wiring film 3 by the wire B702, and the wiring 304 is further connected to the stitch A by the wire B701.
7 and the pad 107 of the lower chip via a stitch A7. Pad 208 of the upper chip, 2
09 and 210 are the pads 108, 10 of the basic lower chip 1 via stitches A8, A9 and A10, respectively.
9 and 110.

The multi-chip package 1 of this embodiment
In order to fabricate the chip 0, as shown in FIG. 2, first, the lower chip 1 is fixed to a package substrate (not shown), and the upper chip 2 is stacked thereon. In the step of laminating the upper chip 2 on the lower chip 1, the metal wiring film 3 is attached to the upper chip 2 in a wafer state before or after the wafer test.

Embodiment 2 This embodiment is another example of the embodiment of the multi-chip package according to the present invention, and FIG. 3 is a perspective view showing the configuration of the multi-chip package of this embodiment. . The multi-chip package 20 of the present embodiment is an example in which the pad arrangement of the upper chip 2 is arranged orthogonal to the direction of the pad arrangement of the lower chip 1, and is basic as shown in FIG. The upper chip 2 includes a lower chip 1, an upper chip 2 mounted on the lower chip 1, and a metal wiring film 3 attached to an upper surface of the upper chip 2. The pin assignment of the multi-chip package 20 corresponds to the basic pad arrangement of the lower chip 1.

The lower chip 1 has a pad row of pads 101 to 106 spaced apart at one edge of the chip surface and a pad row of pads 107 to 110 spaced apart at the other edge. Is provided. The upper chip 2 has pads 201, 202, 203, and 20 spaced apart from one edge of the lower chip 1 orthogonal to the pad row of the chip surface.
7 and 208, and pads 206, 205, 204, 209, and 2 spaced apart on the other edge
And ten pad rows. Further, the multi-chip package 10 has stitches A1 to A10 corresponding to the pads 101 to 110, respectively. The metal wiring film 3 includes metal wirings 302, 303, 304, 305, 307, 30
8 and 309.

The pads 202, 203, and 2 of the upper chip 2
04, 205, 207, 208, and 209 are metal wires 302, 303, 304,
305, 307, 308 and 309, and the metal wirings 302, 303, 304, 305, 307, 308 and 309 are stitched by wires A2, A3, A4,
A5, A7, A8, and A9 are connected to the pads 102, 103, 104, 1
05, 107, 108, and 109.

More specifically, the stitch A6 of the package and the pad 106 of the lower chip 1 will be described in detail.
When connecting the upper chip 2 and the pad 206 of the upper chip 2 arranged on the opposite side of the arrangement direction of the pad 106 of the lower chip 1, the pad 206 of the upper chip and the metal wiring 303 on the metal wiring film 3 are connected by a wire B 602. The connection is made, the wiring 303 is connected to the stitch A6 by the wire B601, and the A6 is connected to the corresponding pad 106 of the lower chip.

[0025]

According to the present invention, a metal wiring film is stuck on the upper IC chip, and desired electrode pads of the upper and lower IC chips are connected to each other through the wiring of the metal wiring film. It is possible to realize a multi-chip package in which IC chips are stacked in a stack structure without restriction on the arrangement direction and arrangement order. For example, even if the arrangement directions of the upper and lower IC chips are orthogonal to each other,
A multi-chip package can be easily realized without increasing the size of the package. Further, assembling of the multi-chip package is facilitated, the degree of freedom in the arrangement and arrangement order of the electrode pads of the mounted IC chip is increased, and the range of responding to market requirements is expanded.

[Brief description of the drawings]

FIG. 1 is a perspective view illustrating a configuration of a multi-chip package according to a first embodiment.

FIG. 2 is a perspective view illustrating a method for manufacturing the multi-chip package according to the first embodiment.

FIG. 3 is a perspective view illustrating a configuration of a multi-chip package according to a second embodiment.

FIG. 4 is an arrangement diagram of electrode pads of a lower chip and an upper chip of a conventional multi-chip package having a stack structure.

FIG. 5 is a pad layout diagram of a lower chip and an upper chip which are not easily manufactured in a conventional multi-chip package having a stack structure.

FIG. 6 is another pad layout diagram of a lower chip and an upper chip which are not easily manufactured in a conventional multi-chip package having a stack structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Multi-chip package of Embodiment 1 1 Lower chip 2 Upper chip 3 Metal wiring film 101-110 Pad of lower chip 201-210 Pad of upper chip 301-309 Wiring A1-A10 Stitch B101-B701 Wire

Claims (6)

[Claims] 1. A multi-chip package in which a plurality of IC chips are stacked in a stack structure, wherein a wiring film having a wiring pattern is formed of two upper and lower IC chips to be interconnected among the plurality of IC chips. IC
Provided on the IC chip surface of the upper IC chip of the chip, at least a part of the electrode pad of the upper IC chip is connected to the corresponding electrode pad of the lower IC chip via the wiring pattern of the wiring film. A multi-chip package characterized by the following. 2. A stitch connected to an electrode pad of the lower IC chip is provided in the multi-chip package, and an electrode pad of the upper IC chip is corresponding to the lower IC chip via the wiring pattern of the wiring film and the stitch. 2. The device according to claim 1, wherein the device is connected to an electrode pad.
A multi-chip package according to item 1. 3. The multi-chip package according to claim 1, wherein the wiring pattern has pads for wire bonding with the electrode pads at both ends. 4. The method according to claim 1, wherein the electrode pads of the upper IC chip are connected to the lower IC chip.
The electrode pads to be connected are arranged in the same direction as the arrangement direction of the electrode pads of the C chip, and
The multi-chip package according to any one of claims 1 to 3, wherein the C chip and the lower IC chip are different. 5. The arrangement according to claim 1, wherein the arrangement direction of the electrode pads of the upper IC chip is a direction orthogonal to the arrangement direction of the electrode pads of the lower IC chip. Multi-chip package. 6. The multi-chip package according to claim 5, wherein the arrangement order of the electrode pads to be connected is different between the upper IC chip and the lower IC chip.