JPS60254267A - Data transfer system - Google Patents

Abstract

PURPOSE:To perform the transfer of data at a high speed and a high degree of freedom by supplying data directly to a RAM of a digital signal processing part from outside with DMA transfer. CONSTITUTION:An address terminal 10 serves as an input terminal through which the address of a RAM4 is supplied when data are supplied to the RAM4 of a DSP (digital signal processing) part from outside, then serves as an output terminal through which the address of an external memory is supplied when the DSP part delivers data to an external memory. A data terminal 1 serves as the input and output terminals of the DSP part and the external memory like the terminal 10. An I/O control part 6 controls the way of transfer of data to outside, and a program control part 5 controls a program for operations of the DSP part. The part 5 also stops the execution of the program with a program stop signal of a DMA mode sent from the part 6 and functions to deliver up an internal bus and the RAM to a DMA action.

Description

DETAILED DESCRIPTION OF THE INVENTION (al industrial application field) The present invention has an internal random access memory (hereinafter referred to as R
Digital signal processing (abbreviated as AM) (hereinafter referred to as D
The present invention relates to an improvement in the data transfer method between an LSI (abbreviated as SP) and the outside.

In recent years, advances in LSI technology have made it easier to perform various digital processes.

For example, there are two methods for band-limiting analog signals: one is analog-based, and the other is digital.

The former limits the analog signal to a predetermined band by passing it through a bandpass filter made up of wire rings, capacitors, etc.

The latter can perform the same function as the former by sequentially storing sampled analog signals in memory, multiplying them by different values, and converting the summed results back into analog signals.

In other words, by changing the values, order, etc. of the four arithmetic operations performed on the digital signal, it is possible, for example, to compress the band of the digital signal or synthesize audio, but the DSP section can perform these four arithmetic operations in real time and at high speed. Since it has the ability to do various things, various processing requests are made at Akane degree.

On the other hand, 1. The degree of integration of SI has increased and it has become one PC.
.

Although it has become possible to include various functions in a package, some of the above requirements cannot be satisfied unless a plurality of DSP LSIs are combined. At this time, data must be transferred between each LSI, but even in such cases, there is a demand for data transfer that can be processed in real time and at high speed.

(bl Conventional technology FIG. 2 shows a conventional example of a block diagram of a DSP section.

In the figure, the DSP section is a calculation section 3. RAM 4. It includes a program control section 5, an input/output control section (hereinafter abbreviated as I10 control) 6, and input and output registers 7 and 8.
When outputting the results of calculations performed by the calculation unit 3 on data on the AM 4 to the outside, there are two typical methods for inputting and outputting data to and from the DSP unit. That is, (1) An input/output register is provided and data is input/output via it.

(The program execution in the 211 DPS unit is stopped, and the RAM in the DSP unit pointed to by the direct memory access counter (not shown) in the program control unit 5 is accessed by direct memory access (hereinafter abbreviated as DAM). to input and output data.

In method (1), for example, the data output from the output register 8 in the #I DSP section is transferred to the #2 DSP with the same configuration.
(not shown).

At this time, data may be lost unless there is a 1:1 correspondence between the sender and the receiver, so this management is done by the main program. However, since the main program also performs other processing, data transfer efficiency deteriorates.

In method (2), when data is added to the output register 8 of the HIDSP section, control of data transfer is separated from the main program and transferred to the I10 control 6, as will be described later.

Therefore, for example, the I10 control units of the #1 and #2 DSP units communicate with each other and transfer data from the aI DSP unit to the #1 and #2 DSP units.
2 Transfer to the DSP section.

#2 When data enters the input register, the flsP section #
2. The program execution is stopped from the l10 control unit in the l5P unit via the program control unit, and the l? indicated by the IIMA counter is stopped. Write the transferred data to the AM address.

In this case, the main program almost never stops (
Although it is possible to transfer a larger amount of data than method 1), the order of data transfer and the RAH address to be written must also be determined in advance.

(C1 Problems to be Solved by the Invention) As mentioned above, among the conventional data transfer methods (11), the main program that controls all the controls in the DSP section controls the data transfer. Transfer efficiency is poor and it is not suitable for transferring large amounts of data at high speed.

Also, method (2) can transfer a large amount of data, but the RAH
There is little flexibility regarding the addresses that can be accessed.

That is, each method has its own problems.

Means for Solving the Td1 Problem The problem described above is that when inputting/outputting data from the outside to the DSP, the RAM included in the DSP section is directly accessed by an address signal via an address bus. The DS
When inputting and outputting data to the RAM with the program execution of the P section stopped and inputting and outputting data to the outside from the DSP section, an address signal is given to the outside from the DSP section and the program is executed at the outside. This problem can be solved by the data transfer method according to the present invention, which inputs and outputs data to and from the outside while the system is stopped.

te1 Effect According to the present invention, when inputting and outputting data to the DSP section, the RAM included in the DSP section can be accessed directly from the outside via the address bus, and
Inputting and outputting data to this RAM is done after stopping the execution of the program in this DSP section.Furthermore, when inputting and outputting data from the DSP section to the external RAM, directly access the external RAM from this 0511 and read the data. Enabled input/output.

In other words, instead of accessing the RAM address specified by the conventional DMA counter, it is now possible to access the RAM directly from the outside via the address bus, allowing for high-speed data transfer with the outside. , RAM can now be accessed flexibly.

(fl Example FIG. 1 (al is a block diagram showing an example of the present invention).

In the figure, the functions of each part are as follows.

(1) Address terminal IO is externally connected to the RAM of the DSP section.
It serves as an input terminal for giving the address of the RAM 4 when inputting data to the memory 4, and serves as an output terminal for giving the address of the external memory when the DSP section outputs data to the external memory. Note that the multiplexer 9 is a part that selects an address signal from the outside or the inside.

(2) Data terminal 1 is D like address terminal 10.
It serves as an input/output terminal between the SP section and the outside.

(The 31110 control unit 6 determines how to exchange data with the outside, that is, when and where to bring the data,
Controls when and where the calculated results are output.

(4) In addition to controlling programs such as calculations in the DSP unit, the program control unit 5 stops program execution in response to a program stop signal (H'ALT signal) during DMA from the I10 control unit, and controls the DMA operation. It operates to pass the internal bus and RAM.

FIG. 1 (bl) is a diagram showing the time chart of FIG. 1(a), and is an example of transferring data from the outside to the DSP unit by DMA.

Therefore, a DM consisting of parts with the above functions
The operation of section A will be explained with reference to FIG.

First, while the osp section is executing program execution address 2, for example, "RE low IN" is added to the I10 control section 6 of the DSP section from the outside. This is D from the outside
This is an input to enable access to the RAM 4 of the SP section.

T10 control unit 6 is R[! When receiving Q-IN''
HALT" is sent to the program control unit 5 to temporarily stop the program execution, and an "OK-0 [IT
” is sent to the outside.

In this state, the external device can access the RAM 4 of the DSP section. That is, control of the RAM 4 of the DSP section is passed to the outside so that it can be performed from the outside, control of the internal data bus 2 is also passed to the outside regarding the RAM 4, and parts related to the program are transferred to the internal data bus. separated from 2.

In this state, an address and R/W-IN'' are applied to the RAM 4 from the outside via the address terminal 10 and the multiplexer 9 in response to reading and writing.

In addition, "R/W -IN" indicates reading when it is 1, writing when it is O, and when writing, it is the clock input for writing "-TC
IJ-IN'' and write at the rising edge of this clock.

Thereafter, data is input/output via terminal 1 connected to data bus 2.

Next, the operation when transferring data from the DSP unit to the outside will be described, and the case where the same DSP unit is located outside will be described.

Figure 1 (C) shows #1 n5ps section and #2 DSP.
A connection diagram for transmitting and receiving data between U and 7 is shown.

Figure 1 (dl is a time chart for explaining the operation of Figure 1 (C1), a
An example of inputting and outputting data by controlling the 32 units is shown below.

First, prior to data input/output, a signal "REQ-0UT" indicating input is output to the a DSP section in the same manner as described above. “0K-” from the 12,032 copies sent out in response to this
OUT” is input to the #I DSP unit 17) OK-IN.

After outputting "REQ -0UT", a l DS
The P section receives "0K-IN" indicating that the program execution has been stopped due to the sending of "HALT" in the #2 DSP section.
” is input to the SP section #21).

“0K-IN” is returned from 12032 copies, #2
After the control of the DSP unit is transferred to the control of the a I DSP unit, the address is sent to the RAM in the #2 DSP unit via the address terminal and input/output via the data bus.

FIG. 1 (el indicates another embodiment).

As shown in the figure, when the DSP LSI operates alone, the external RAM 11 is sent to a normal address and chip enable (CE) via this address terminal 10.

It can also be set to be controlled by write enable (row).

That is, the method of the present invention eliminates the input/output register and allows data to be directly input/output from the outside to the RAM of the DSP section by DM^ transfer, so data can be transferred at high speed and with a degree of freedom.

(As explained in detail in the g1 invention, according to the present invention, the D
Data can be transferred to and from the SP section at high speed and efficiently.

[Brief explanation of the drawing]

Figure 1 (al is a block diagram showing an example for implementing the present invention, Figure 1) is a time chart diagram of Figure 1+a), Figure 1 (C1 is a block diagram showing another embodiment of the present invention) A block diagram, FIG. 1(d) is a time chart diagram of FIG. 1 (C1, 1) FIG. 1(e) is a block diagram showing another embodiment of the present invention,
FIG. 2 shows a block diagram of a conventional example. In the figure, 1 and 10 are terminals, 2 is an internal data bus, 3 is an arithmetic unit, 4 is a RAM, 5 is a program control section, 6 is an I10 control section, and 9 is a multiplexer. 2

Claims (1)

[Claims] In a method of transferring data between a digital signal processing unit that has an internal random access memory and the outside, when inputting and outputting data from the outside to the digital signal processing unit, it is necessary to A random access memory is directly accessed by an address signal via an address bus, data is input/output to the random access memory while program execution of the digital signal processing unit is stopped, and the digital signal processing is performed. When inputting/outputting data from the unit to the outside, an address signal is given to the outside from the digital signal processing unit, and the data is input/output to the outside while program execution on the outside is stopped. Data transfer method.