JPS60253240A - Method for evaluation of semiconductor device - Google Patents

Method for evaluation of semiconductor device

Info

Publication number
JPS60253240A
JPS60253240A JP11175584A JP11175584A JPS60253240A JP S60253240 A JPS60253240 A JP S60253240A JP 11175584 A JP11175584 A JP 11175584A JP 11175584 A JP11175584 A JP 11175584A JP S60253240 A JPS60253240 A JP S60253240A
Authority
JP
Japan
Prior art keywords
semiconductor device
thermal stress
semiconductor chip
state
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11175584A
Other languages
Japanese (ja)
Inventor
Tomoharu Yamauchi
山内 智晴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11175584A priority Critical patent/JPS60253240A/en
Publication of JPS60253240A publication Critical patent/JPS60253240A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To enable to easily evaluate a semiconductor device under various condition by a method wherein the semiconductor device is brought in a current- applied state, and thermal stress is added by the generation of heat by itself. CONSTITUTION:The resistance value between a socket 2 and the lead 5 of a semiconductor device 4 is measured using a resistance meter. Then, when voltage is applied to a semiconductor chip 7 and an operating circuit 11 by giving an ON state to a switch 13, the semiconductor chip 7 is turned into the state of operation. At this time, Joule heat is generated on the semiconductor chip 7 is proportion to the degree of consumption of power, and the semiconductor device 4 generates heat by itself, thereby enabling to give thermal stress to the lead 5 and a connecting terminal 3. Then, when the switch 13 is turned OFF, the semiconductor chip 7 and the operating circuit 4 are brought into a non- operational state, and the semiconductor device 4 stops the genera-of heat by itself. A thermal change is given between the lead 5 and the connecting terminal by repeating the make and break operation of the switch 13 as above-mentioned, and the change of contact resistance by thermal stress can be evaluated by repeating a resistance measurement, a current-applied state and a non-operational state.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、半導体装置をソケットに挿入した場合の熱
ストレスによる接触抵抗の変化を応用した半導体装置の
評価方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for evaluating a semiconductor device that applies changes in contact resistance due to thermal stress when the semiconductor device is inserted into a socket.

〔従来技術〕[Prior art]

従来のこの種の評価方法として、第1図に示すものがあ
った。この図において、1は基板、2はこの基板IK接
着され、たソケット、3はこのソケット2に付属してい
る接触端子、4は前記ソケット2に挿入したインチリー
ドされていない半導体装置、5はこの半導体装置4のリ
ード、6は前記接触端子3およびリード5にそれぞれ取
り付けられた検出端子である。
A conventional evaluation method of this type is shown in FIG. In this figure, 1 is a board, 2 is a socket that is IK-bonded to this board, 3 is a contact terminal attached to this socket 2, 4 is a semiconductor device without inch leads inserted into the socket 2, and 5 is a Leads 6 of this semiconductor device 4 are detection terminals attached to the contact terminals 3 and leads 5, respectively.

次に従来の評価方法について説明する。基板1にソケッ
ト2を接着後半田付けにより固定する。
Next, a conventional evaluation method will be explained. The socket 2 is fixed to the board 1 by adhesive and soldering.

このソケット2に半導体装置4を挿入後、接触端子3と
リード5に検出端子6を半田付けする。それぞれの検出
端子6間の抵抗を抵抗計で測定する。
After inserting the semiconductor device 4 into the socket 2, the detection terminal 6 is soldered to the contact terminal 3 and the lead 5. The resistance between each detection terminal 6 is measured with a resistance meter.

この値がソケット2の接触端子3と半導体装置4のリー
ド5との接触抵抗である。
This value is the contact resistance between the contact terminal 3 of the socket 2 and the lead 5 of the semiconductor device 4.

次に基板1を高温保存用装置、および低温保存用装置に
交互に入れることを繰り返すことKよる温度サイクルで
、ソケット2および半導体装置4に熱ストレスを加える
Next, thermal stress is applied to the socket 2 and the semiconductor device 4 through a temperature cycle in which the substrate 1 is alternately placed in a high-temperature storage device and a low-temperature storage device.

ソケット2および半導体装置4に熱ストレスが加えられ
れば、接触端子3とリード5の材質およびメッキの違い
により、線膨張係数が異なり、接触部分にずれを生じる
。これを繰り返すことKより接触部分の導電度が劣化し
、抵抗が増加する。
If thermal stress is applied to the socket 2 and the semiconductor device 4, the linear expansion coefficients will differ due to the difference in the materials and plating of the contact terminals 3 and the leads 5, resulting in misalignment of the contact portions. By repeating this, the conductivity of the contact portion deteriorates and the resistance increases.

このように従来は、検出端子6間の抵抗測定。In this way, the conventional method is to measure the resistance between the detection terminals 6.

温度サイクルを繰り返し実施することにより、熱ストレ
スによる接触抵抗の変化を検出し半導体装置の評価をし
ていた。
By repeatedly performing temperature cycles, semiconductor devices were evaluated by detecting changes in contact resistance due to thermal stress.

上記従来の方法では、半導体装置4とソケット2に熱ス
トレスを加えるため、高温保存用の装置と低温保存用の
装置とに交互に入れかえる作業が必要であり、作業性に
劣るという欠点があった。
In the conventional method described above, in order to apply heat stress to the semiconductor device 4 and the socket 2, it is necessary to alternately replace the equipment with a high-temperature storage device and a low-temperature storage device, which has the disadvantage of poor workability. .

〔発明の概要〕[Summary of the invention]

この発明は、上記のような欠点をなくすためになされた
もので、半導体装置を通電状態iCして、自己発熱させ
ることで熱ストレスを加えることKより、評価できる方
法を提供することを目的としている。以下この発明を図
面について説明する。
This invention was made in order to eliminate the above-mentioned drawbacks, and the purpose is to provide a method that can evaluate a semiconductor device by putting it in an energized state (iC) and applying heat stress by causing self-heating. There is. The present invention will be explained below with reference to the drawings.

〔発明の実施例〕[Embodiments of the invention]

第2図はこの発明の一実施例を示すもので、16ピンデ
ユアル・ライン・パッケージを例にした樹脂封止形の半
導体装置の評価例である。第2図において、1〜6は第
1図と同じものであり、1は前記半導体装114に収納
されているICチップ等の半導体チップ、8はこの半導
体チップ1とy−ド5とを接続している内部金属細線、
9は前記半導体チップTを接続したり一ド5以外のり一
ド5を1ピンおきに内部金属細線または外付けで金属線
を用いて接続した接続線、10は接続されていないピン
どうしを接触端子3側で接続した外付は配線で、この外
付は配線10の両9aK検出端子6が摩り付けられてい
る。11は前記半導体チップ7を動作させるために基板
1上に配線した固体抵抗器等より構成された動作回路、
12は前記半導体チップ1および動作回路11の電源、
13はこの電源12を制御するスイッチである。
FIG. 2 shows an embodiment of the present invention, and is an evaluation example of a resin-sealed semiconductor device using a 16-pin dual line package as an example. In FIG. 2, numerals 1 to 6 are the same as in FIG. There is a thin metal wire inside,
Reference numeral 9 indicates a connection line connecting the semiconductor chip T or connecting every other pin of the semiconductor chip T using an internal thin metal wire or an external metal wire, and 10 a connection line that connects unconnected pins to each other. The external connection connected on the terminal 3 side is a wiring, and both 9aK detection terminals 6 of the wiring 10 are attached to this external connection. Reference numeral 11 denotes an operating circuit composed of solid resistors and the like wired on the substrate 1 in order to operate the semiconductor chip 7;
12 is a power supply for the semiconductor chip 1 and the operating circuit 11;
13 is a switch that controls this power supply 12.

次に動作について説明する。Next, the operation will be explained.

従来と同じように検出端子6間の抵抗を、抵抗計で測定
することによりソケット2と半導体装置4のリード5間
の抵抗値を測定する。次にスイッチ13を閉じることに
より、電圧を半導体チップ7および動作回路11に印加
すると、半導体チップ7は動作状態となる。この時消費
電力に応じて半導体チップ1がジュール熱を発生し、半
導体装置4は自己発熱しり一ド5と接触端子3に熱スト
レスを与えることができる。
As in the conventional case, the resistance value between the socket 2 and the lead 5 of the semiconductor device 4 is measured by measuring the resistance between the detection terminals 6 with a resistance meter. Next, by closing the switch 13, a voltage is applied to the semiconductor chip 7 and the operating circuit 11, and the semiconductor chip 7 enters the operating state. At this time, the semiconductor chip 1 generates Joule heat in accordance with the power consumption, and the semiconductor device 4 can apply thermal stress to the self-heating shield 5 and the contact terminals 3.

次にスイッチ13を開放すれば半導体チップ1゜動作回
路11は停止状態になり、半導体装置4は自己発熱を停
止する。以上のようにスイッチ13の開閉を繰り返すこ
とKより、リード5と接触端子3間に熱変化を与えるこ
とで、熱ストレスを加えられる。抵抗測定と、通電状態
、停止状態を繰り返すことで、熱ストレスによる接触抵
抗の変化が評価できる。
Next, when the switch 13 is opened, the semiconductor chip 1° operation circuit 11 is brought to a halted state, and the semiconductor device 4 stops self-heating. By repeatedly opening and closing the switch 13 as described above, thermal stress is applied by causing a thermal change between the lead 5 and the contact terminal 3. By repeating resistance measurement, energized state, and de-energized state, changes in contact resistance due to thermal stress can be evaluated.

そして、電圧値、および動作回路11の負荷抵抗等の値
を変化するととKより、自己発熱量をコントロールし、
種々の条件が設定できる。また、外付は配線10.検出
端子6の接続ピンをかえることKより、任意のピン間の
変化が評価できる。
Then, by changing the voltage value and the values of the load resistance of the operating circuit 11, the self-heating amount is controlled by K,
Various conditions can be set. Also, external wiring is 10. By changing the connection pins of the detection terminal 6, changes between arbitrary pins can be evaluated.

なお、上記実施例では樹脂封止形の半導体装置4につい
て述べたが、自己発熱による熱ストレスを応用したもの
で、樹脂封止形のみならず、リードとソケットにより接
続する半導体チップてに適用することができる。
In the above embodiment, a resin-sealed type semiconductor device 4 was described, but the thermal stress caused by self-heating is applied, and it is applicable not only to resin-sealed type but also to semiconductor chips connected by leads and sockets. be able to.

また、基板1上Vc4i数の回路を作成し、動作回路1
1の条件をかえることにより、一度で複数の熱ストレス
条件の評価を実施できる。
In addition, the number of circuits Vc4i is created on the board 1, and the operating circuit 1
By changing the first condition, it is possible to evaluate multiple heat stress conditions at once.

〔発明の効果〕〔Effect of the invention〕

以上説明したようにこの発明は、外部電源のオン、オフ
により半導体チップを動作せしめて半導体装置を自己発
熱させ、半導体装置のリードとソケットの接触端子との
接触抵抗を測定し半導体装置の評価をするようにしたの
で、従来のように高温、低温保存用の装置を使用するこ
となしに複数の熱ストレスを与えることができ、容易に
種々の条件における評価ができる効果が得られる。
As explained above, the present invention operates a semiconductor chip by turning on and off an external power supply to cause the semiconductor device to self-heat, and evaluates the semiconductor device by measuring the contact resistance between the leads of the semiconductor device and the contact terminals of the socket. As a result, multiple thermal stresses can be applied without using conventional high-temperature and low-temperature storage devices, and the effect of easily evaluating under various conditions can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の評価方法を示す半導体装置あ側面図、第
2図はこの発明の一実施例による評価方法を示す半導体
装置の側面図であ・る。 図中、1は基板、2はソケット、3は接触端子、4は半
導体装置、5はリード、6は検出端子、1は半導体チッ
プ、8は内部金属細線、9はリードの接続線、10は外
付げ配線、11は動作回路、12は電源、13はスイッ
チである。 なお、図中の同一符号は同一または相当部分を示す。 代理人 大岩増雄 (外2名) 第1図 第2図
FIG. 1 is a side view of a semiconductor device showing a conventional evaluation method, and FIG. 2 is a side view of a semiconductor device showing an evaluation method according to an embodiment of the present invention. In the figure, 1 is a board, 2 is a socket, 3 is a contact terminal, 4 is a semiconductor device, 5 is a lead, 6 is a detection terminal, 1 is a semiconductor chip, 8 is an internal thin metal wire, 9 is a lead connection line, and 10 is a External wiring, 11 is an operating circuit, 12 is a power supply, and 13 is a switch. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 半導体装置をソケットに装着した時に、前記半導体装置
に熱ストレスを加え、そのリードと前記ソケットの接触
端子間の接触抵抗の熱ストレス変化を測定し評価する方
法において、前記半導体装置を通電状態にすることによ
る自己発熱を応用して前記熱ストレスを加え、所要の評
価を行うことを特徴とする半導体装置の評価方法。
In the method of applying thermal stress to the semiconductor device when the semiconductor device is mounted in a socket, and measuring and evaluating a thermal stress change in contact resistance between the lead and the contact terminal of the socket, the semiconductor device is brought into an energized state. A method for evaluating a semiconductor device, characterized in that the thermal stress is applied by applying self-heating due to heat generation, and necessary evaluation is performed.
JP11175584A 1984-05-29 1984-05-29 Method for evaluation of semiconductor device Pending JPS60253240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11175584A JPS60253240A (en) 1984-05-29 1984-05-29 Method for evaluation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11175584A JPS60253240A (en) 1984-05-29 1984-05-29 Method for evaluation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60253240A true JPS60253240A (en) 1985-12-13

Family

ID=14569361

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11175584A Pending JPS60253240A (en) 1984-05-29 1984-05-29 Method for evaluation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60253240A (en)

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