JPS60252958A - 論理回路の試験方式 - Google Patents
論理回路の試験方式Info
- Publication number
- JPS60252958A JPS60252958A JP59109936A JP10993684A JPS60252958A JP S60252958 A JPS60252958 A JP S60252958A JP 59109936 A JP59109936 A JP 59109936A JP 10993684 A JP10993684 A JP 10993684A JP S60252958 A JPS60252958 A JP S60252958A
- Authority
- JP
- Japan
- Prior art keywords
- data
- input
- output
- scan
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59109936A JPS60252958A (ja) | 1984-05-30 | 1984-05-30 | 論理回路の試験方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59109936A JPS60252958A (ja) | 1984-05-30 | 1984-05-30 | 論理回路の試験方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60252958A true JPS60252958A (ja) | 1985-12-13 |
JPS64730B2 JPS64730B2 (enrdf_load_stackoverflow) | 1989-01-09 |
Family
ID=14522860
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59109936A Granted JPS60252958A (ja) | 1984-05-30 | 1984-05-30 | 論理回路の試験方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60252958A (enrdf_load_stackoverflow) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6675333B1 (en) | 1990-03-30 | 2004-01-06 | Texas Instruments Incorporated | Integrated circuit with serial I/O controller |
US6898544B2 (en) | 1988-09-07 | 2005-05-24 | Texas Instruments Incorporated | Instruction register and access port gated clock for scan cells |
US6959408B2 (en) | 1989-06-30 | 2005-10-25 | Texas Instruments Incorporated | IC with serial scan path, protocol memory, and event circuit |
US6975980B2 (en) | 1998-02-18 | 2005-12-13 | Texas Instruments Incorporated | Hierarchical linking module connection to access ports of embedded cores |
US7058862B2 (en) | 2000-05-26 | 2006-06-06 | Texas Instruments Incorporated | Selecting different 1149.1 TAP domains from update-IR state |
-
1984
- 1984-05-30 JP JP59109936A patent/JPS60252958A/ja active Granted
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6898544B2 (en) | 1988-09-07 | 2005-05-24 | Texas Instruments Incorporated | Instruction register and access port gated clock for scan cells |
US6959408B2 (en) | 1989-06-30 | 2005-10-25 | Texas Instruments Incorporated | IC with serial scan path, protocol memory, and event circuit |
US6990620B2 (en) | 1989-06-30 | 2006-01-24 | Texas Instruments Incorporated | Scanning a protocol signal into an IC for performing a circuit operation |
US6996761B2 (en) | 1989-06-30 | 2006-02-07 | Texas Instruments Incorporated | IC with protocol selection memory coupled to serial scan path |
US7058871B2 (en) | 1989-06-30 | 2006-06-06 | Texas Instruments Incorporated | Circuit with expected data memory coupled to serial input lead |
US6675333B1 (en) | 1990-03-30 | 2004-01-06 | Texas Instruments Incorporated | Integrated circuit with serial I/O controller |
US6975980B2 (en) | 1998-02-18 | 2005-12-13 | Texas Instruments Incorporated | Hierarchical linking module connection to access ports of embedded cores |
US7058862B2 (en) | 2000-05-26 | 2006-06-06 | Texas Instruments Incorporated | Selecting different 1149.1 TAP domains from update-IR state |
Also Published As
Publication number | Publication date |
---|---|
JPS64730B2 (enrdf_load_stackoverflow) | 1989-01-09 |
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