JPS60252958A - Testing system of logical circuit - Google Patents

Abstract

PURPOSE:To shorten time for checking data inputting/outputting operation of input/output terminals and to reduce the number of connecting lines by providing scan flip-flop in each input/output circuit unit. CONSTITUTION:Scan flip-flops 35a-35c are provided in each input/output circuit unit (IOU)31, and necessary data are transmitted in series using small number of connecting lines to the flip-flop by scan in system, and distributed one by one by a decoder 34. Increase of time required for transmission in series makes distribution in series of data by scan in system in the second test controlling section 3a during scan in operation timing of the first test controlling section 2 possible by conditional expression of the number of normal data input/output terminals < the number of flip-flops of the object to be tested. Thus, the time for test does not increase by the reduction of the number of connecting lines.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a logic circuit, particularly a highly integrated circuit element (LSI) having a scan-in/out function, or a plurality of logic circuit elements or an LSI integrated circuit having the scan-in/out function. This paper relates to a test method for logic circuits in intermediate packaging structures.

Traditionally, dental data processing systems have been constructed using logic (ro) circuits, but in recent years, with the development of semiconductor integration technology in particular, many logic circuit elements using semiconductors, such as microprocessors (MPUs), have become capable of implementing complex functions in one package. Logic circuits are functionally similar to combinational circuits such as Noah and Nando. A latch obtained by interconnecting an element and a plurality of combinational circuits
Arithmetic functions, data retention, and data transfer functions realized by combining sequential circuits such as registers and flip-flop circuits (FF) constitute a data processing system such as a central processing unit (CPU).

In order to improve reliability and maintainability, data processing systems such as this are equipped with functions such as parity check, automatic error correction, retry, and self-diagnosis. In order to easily point out the normality or failure location, data input from these input terminals (P
i) Or, apart from the data output (PO) from the output terminal, data can be read out (scan out) at any position of the FF constituting the LSI or intermediate packaged body, or data can be written to any position (scan 42 means is widely used) It is well known that he is a stranger.

[Conventional technology]

Conventionally, the above-mentioned scan-in/out test methods have been broadly classified into shift register method and address method, and in both cases, ■ scan-in, @ P i /P.

The logic operation is performed in the following order: O scanout.

FIG. 2(a) shows a configuration side port of an LSI/intermediate mounting body to be tested which is equipped with a scan-in/out function using an addressing method in the prior art and in one embodiment of the present invention.

Figure 2(b) shows the connection contingencies of a flip-flop circuit (FF) with a scan-in/out function, which is the target unit for scan-out, and Figure 3 is a block diagram of a conventional logic circuit testing method using an addressing method. Show the button.

Test subject 1 i′ in prisoner 3! This is an image of an intermediate package such as a printed wiring board composed of an LSI or a plurality of LSIs, and the number n of FFIs to 11 to be scanned in/out reaches several tens to several 1ρOO,
Each FF has address data (Sadl=m) 1 selector (
Apply the (Si) selection signal to MPX) and send the selection signal. Congratulations. =2y''- FFs associated with a d t-1c are selected one by one, and the scan-in data storage unit (S
i-data MEM) data from 21a, separate test object l
A scan in cycle set to the selected FF is executed in accordance with a scan inset timing signal (CLK) applied to the CLK terminal of the selected FF.

Here, each buffer BUFF for transmitting data to the test object l from the first test control fl12 is shown as a single unit, but BUFFK in the SadIS-m diagram is composed of m BUFFs corresponding to m bits. After this scan-in operation, the second test control unit 3 sends input or output expected value data to all data input terminals Pil to q of the device under test 1 via the input/output circuit unit (IOU) column. The test input data (Pi) of the storage unit (Pi/Po data storage M) 32b is applied in parallel and sent from the input/output control data storage unit (input/output control data MEM) 32a that holds input or output selection instruction data. At least that l0U
The selection terminal of the tri-state circuit (TSL) of 31 (as well as the output obtained from all the data output terminals Po+ to r) is applied to the exclusive OR circuit (FOR) of the YIOU 31 through the B UFFχ and output expected value data storage unit. (Po data MEM) 21b and applied to the output AND circuit (AND) gated by the mask data from the valid/invalid instruction data storage section (Po mask data MEM) 32c to determine the match at the valid EOH. Causes a mismatch signal to be sent.

Although the input terminal Pixxq and output terminals pol to r in FIG. 2 (al) are shown as dedicated terminals, l0U31 shown in FIG. shall be.

In this way, the Pi/Po data M by the second test control section 3
After the test using data input/output from the EM32b, the first test control unit 1 returns the FFI-n of the test object 1 to the scanout state (So) from the scanout address unit 22b.
Address data (S
a d 1-h) is scanned out by the application of the scan signal (SO), and the scan-out expected value data storage unit (So data MEM) is generated by J of the control unit 1.
Scan-out valid/invalid instruction data storage unit (So mask data MEM) 2]c by comparing with the data of
The mask data allows the gate to send a valid error signal.

[Problem that the invention seeks to solve]

As described above, the scan-in/out operation is a scan-in cycle in which the first test control unit 2 writes Si data in series to the FFI-n, and a data input/output cycle to all input/output terminals by the second test control unit 3. and S by the first test control section 2.

Scanout cycle with serial readout of data? Execute.

Here, the operation by the first test control unit 2 can be performed by connecting four to ten signal lines, but each scan-in and scan-out cycle requires a number of steps equal to the number N of FFs, and conversely, the second test The data input/output operation by the control unit 3 takes only about 2 steps, but the number of connection lines 39, excluding 7 for error signals, is in the example close to the test object 1, and is installed in the bin element part. l0
The number of connection wires between U31 and other circuits of the second test control section 3 remaining on the test equipment main body side is 390, for example, the number of input/output terminals or 102.
If there were 4 wires, it would have required 3,072 wires.

This means that the input/output control data MEM 32 a, Pl
/Po data MEM32b, Po? School data MEM3
2c as well, it is necessary to allocate storage areas in advance in accordance with the number of terminals, so these storage areas may be prepared in vain depending on the situation.

In response to such diversification, it is desirable that the number of connection lines be as small as possible in a test method or test apparatus that tests such LSIs or intermediate mounted bodies, and that the storage area be allocated to 6 units. The present invention aims to provide a logic circuit testing method that solves the above problems.

[Means to solve problems]

This purpose is that the second test control section has a means for selectively applying input data bit 7', a means for receiving output data bit Y, and a means for comparing output data bit v with expected value data bit during the data input/output operation. The input/output circuit unit y is provided corresponding to the input/output terminal of the test object, and each input/output circuit unit is equipped with control data bits for instructing input or output operation selection, input or output expected value data bits, and collation/comparison data bits. A 3-bit parallel register that temporarily holds the mask data pitton that indicates whether it is valid or invalid.
The second test control section is equipped with a set of three scan-in flip-flop circuits that receive each data bit to be transferred to the register, and decoding means that selects the flip-flop circuits one by one. At the timing of the scan-in operation executed by the control section, a set of three input/output control data, input or output expected value data, and mask data held in a separately provided storage means are each stored by a decoding means corresponding to the input/output circuit unit. select and scan in the flip-flop circuits one by one, and upon completion of the scan-in operation of the first test control section, transfer the data to each register of the flip-flop circuit and apply it to the input/output circuit unit; In accordance with the input/output control data in each register, the input/output circuit unit v applies human data to the input terminal of the pitton under test, and the output data obtained at the output terminal is determined by the comparison means in the pitton input/output circuit unit. It is compared with the expected value data bit, and the mismatch signal wWk of the comparison result is detected as a total error in the data input/output operating pressure. The feedback holding signal of the flip-flop circuit is sent out by the address scan operation performed by the decoding means Z at the scan-out timing of the first test control section, which is subsequently executed, and a mismatch signal is obtained. This is achieved by providing the present invention which identifies output terminals.

[Effect]

According to the present invention, the signal applied to the data input/output terminal of the test object by the second test control section is provided around the input/output terminal.
Instead of directly distributing data by three times the number of connection lines corresponding to 0U31, scan F for each 10U31
The F units transmit necessary data serially to the FF using a scan-in method using a small number of access lines, and are distributed one by one by a decoding means.

The increase in time due to serial transmission is usually equal to the number of data input/output terminals multiplied by the number of FFs of the device under test. By carrying out the distribution test, the objective is to obtain a test method that maintains the actual test time at the same level as conventional test methods while effectively reducing the number of connection lines to the device under test.

〔Example〕

An embodiment of the present invention will be explained below with reference to the drawings.

FIG. 1 1bl is a block diagram of a logic circuit testing method according to an embodiment of the present invention, and FIG. 1 1bl is a time chart showing the operation timing 7 thereof.

The same reference numerals indicate the same objects throughout the drawings. Therefore, the test object and the first test control section 2 are the same as before, and the input/output circuit unit 1-IOU31 of the second test control section 3a is also the same as before.

In one embodiment of the present invention, as described in the summary of the two tops, the scan input of the first test control section 2 is different from the conventional method in which a direct connection line was used for inputting and outputting data for each input/output terminal, that is, for each corresponding l0TJ31. During the cycle, the second test control unit 3
A also differs in that the input/output terminal address section 33 distributes signals one by one to the newly provided scan FFs 35 a + b + C via the decoder 34 using the scan-in method.

The decoder 34 scans the scan FF3 corresponding to l0U31 according to the address signal Sad■ of the input/output terminal address section 33.
5a, b, cy are selected one by one and input/output control data MEM3
2 a a + Input or output expected value data storage unit (P
5ii10■ of input/output control data from the i/Po data MEM) 32bb and the valid/invalid instruction data storage section (Po mask data MEM) 32cc.

Scan in SiD of Pj/Po data and Sixσ)t of PO mask data. In addition, selector (MPX) 3
7 selects SixωY at this timing. It is 0.0 with the time chart of the first edition).

Normally, the number of input/output terminals is the F of the scan-in target of the test device 1.
The set timing CLKσ) for each data to FF35a=c is the scan inset timing (CLK) in the first test control unit 2, that is, the scan inset timing (CLK) in FIG.
If this is the same as e, the scan-in of the second test control section 3 will be completed in a shorter time than that of the first test control section 2.

It waits for the scan-in of the first test control section 2 to finish, and upon its completion, the Pi/Po set timing signal and the data of all signal digit registers 36a=c scan m35a=c are transferred to the corresponding register all at once.

Here, input χ is indicated by 5ii10σ). For example, 1
The register 36a, which was set to 1'', is set to TSL 'f on, and the input data SiDσ), which was set to the register 36b&Ci, is changed to the input terminal PiKt of the test object 1 by ■.
JJ kasa ttb.

Therefore, the output data of the device under test 1 is transmitted to the output terminal P, whether there is a delay in the internal logic circuit of the device under test 1 or not.

is obtained and applied to EOR via BUFF of l0U31. At this time, 0'' is set in S i Ilo ffl to specify the output, and the register 36b corresponding to the other register 36a has the Pi/Po total MFM 32.
Output expected value data Po from bb or scan FF35b
Qpi/Po Lumi/Po set timing data from 3
6b, and the PO register 36c is similarly obtained.
Since the mask data MEM32cc (SIXσ) is set, the output data of the test object 1 is the expected output value data P at EOR.

, and in the AND operation, a match/mismatch signal gated as a valid signal is output.

The match/mismatch signal is cascaded with the signal BUF'F
It is configured to obtain a logical sum on the output side, and if there is a mismatch signal, it is detected as a total error signal as shown in (■).

On the other hand, the AND output obtained from the mismatched signal is the corresponding 71
+ Let MPX37 do the work for you. At this time, the delay circuit ■L) 37
The error set timing α (9) is delayed by 1 and is applied to MPX37 as 00, and the mismatch signal is F.
Set to F35c.

At this point, the system clock is applied, and the first test control section 2 executes a scan-out cycle and returns to 5oF.
Sad+ to m are sent one by one from the F address section 22b, and the contents of FFIM-n in the test object 1 are output one by one, and the scan-out check (2) is executed by comparing and matching/masking operations as in the conventional method.

In the second test control section 3, during the execution of the scan out cycle by the first test control section 2, the input/output terminal address section 33 again sends the scan FF 35a=c via the decoder 34.
The check bin data SomY is scanned out one by one, and a mismatch signal is sent out from AND, and y, :1ou3i, that is, the output terminal is identified.

As described above, the timing for scanning in/out of each data scan FF 35a=c in the second test control unit 3 is determined during the scan in/out cycle period by the first test control unit 2 after the end of the data input/output cycle. Therefore, the test time in the data input/output cycle of the second test control section 3 is the same as that of the conventional method (tests can be executed by scanning in/out of the test object I in a test time comparable to that of the conventional method).

Moreover, compared to the conventional case, the number of connection lines for input/output data to the device under test 1 is reduced from the conventional connection line 39 to the scan FF 35a=c.
Since it is replaced with the scan-in connection line 39a to
For example, the conventional connection wire 39 is the aforementioned 1.024 wires x 3 = 3
, 072 to 3 connection lines 39a, and 10 lines due to 1,024=210 from the decoder 34 and 3 timing signal lines, resulting in a total of 16 lines.
The number of connecting wires χ in the section requiring long route interruption in the test control section 2 can be significantly reduced.

In addition, input/output control data MEM32 a a, P i
/P.

Data MEM32bb and Po mask teddy M3
Since the data stored in the 2cc can be transmitted serially from one output means according to the scan-in/out order, there is no need to provide 1024 circuits for each data output means, and the secondary effect is that the storage area can be used efficiently. can get.

Although the above explanation was based on scan-in/out using the address method, it is also possible to perform the test by scan-in/out of the test object 1 by configuring the first or/and second test control section using another soft register method. It is obvious to do so.

〔Effect of the invention〕

As explained above, according to the present invention, since the data input/output operation targets +7 input/output terminals of the conventional device under test, the connection line a can be significantly reduced without increasing the test time compared to the conventional method. It is possible to provide an efficient logic circuit testing method that can easily accommodate the diversity of test objects.

[Brief explanation of drawings]

FIG. 1 (al is a block diagram of the logic circuit test method in one embodiment of the present invention, the first cause) is a time chart showing its operation timing, and FIG. Figure 2(b) is a side view of the structure of the test object, and Figure 2(b) is a connection side view of a flip-flop circuit (FF) having 4 scans and 91 functions. The block diagram is shown below. In the figure, 1 is the test object, 2 is the first test control section, 3, 3a is the wJ2 test control section, 21a
is skin + nii 7f' - evening 1etl'1lli (Sif
21b is a scan-out expected value data storage section (So data MEM), 21C is a valid/invalid instruction data storage section (So mask data MEM), 22a is a scan-in FF address section, and 22b is a scan-out FF
Address section, 23 is a selector (MPX), 31 is an input/output circuit unit (IOU), 32a is an input/output control data storage section, 32b is an input or output expected value data storage section (P
i/Po data MEM), 32c is a valid/invalid instruction data storage section (Po mask data m), 33 is an input/output terminal address section, 34 is a decoder, and 353 to c are scan-in F
F 136 a S-c is Lenstar, 37 is selector (M
PX), and 39.39a are connection lines.

Claims (1)

[Scope of Claims] A first test control unit that scans data bits in and out of each flip-flop circuit in a logic circuit of a test object and compares them with first expected value data corresponding to the scan-in data; A second test control section applies other test data to the data input terminal and compares the output data obtained at the data output terminal with second expected value data, and scans in. There is a scan-in/out test system that performs data input/output and scan-out and performs a functional test on the test object based on the comparison results obtained from both control units, and the second test control unit performs the data input/output operation. An input/output circuit unit consisting of means for selectively applying input data bits, means for receiving output data pittons, and means for comparing output data pittons with expected value data bits is equipped corresponding to the input/output terminals of the +-V test object. and 3 bits that temporarily hold control data bits for instructing input or output operation selection, input or output expected value data bits, and mask data bits for instructing validation/invalidity of verification comparison for each input/output circuit unit. The second test control section comprises a parallel register, a set of three scan-in flip-flop circuits that receive each data bit to be transferred to the register, and decoding means for selecting the flip-flop circuits one by one. At the timing of the scan-in operation executed by the first test control section, the input/output control data, input or output expected value data, and mask data held in a separate storage means are respectively decoded by the decoding means into three corresponding to the input/output circuit units. A set of flip-flop circuits are selected one by one and scanned in, and upon completion of the scan-in operation of the first test control section, data is transferred to each pitton core register of the flip-flop circuit and applied to the input/output circuit unit. The input/output circuit unit outputs the input data bits according to the input/output control data in each register.
At the same time as applying voltage to the input terminal of the test object, the output data pit obtained at the output terminal is compared with the expected value data bit by the comparison means in the input/output circuit unit, and the difference signal of the comparison result is ORed to output the data output. While it is detected as a total error in the operation, the coincidence/mismatch signal in the input/output circuit unit is fed back to one of the corresponding flip-flop circuits and held, and the decoding means is activated at the scan-out timing of the first test control section to be subsequently executed. 1. A testing method for a logic circuit, characterized in that an output terminal Z from which a mismatch signal is obtained is identified by sending out a feedback holding signal of the flip-flop circuit through an address scan operation performed by the flip-flop circuit.