JPS6025276A - Forming method of gate of field-effect type transistor - Google Patents

Abstract

PURPOSE:To increase the mutual conductance of an MES.FET with a III-V group compound semiconductor active layer by exposing the surface of a III-V group compound semiconductor in a plasma atmosphere containing iodine ions and forming a metallic film on the surface of the semiconductor through an evaporation method or a sputtering method. CONSTITUTION:An SiO2 film 13 is formed on a semiconductor active layer 12 at a substrate temperature of 320 deg.C, and a positive type resist 14 is applied. The resist film 14 is processed through a photo-lithography method, and SiO2 13 is processed by a buffer solution consisting of fluoric acid and an ammonium fluoride aqueous solution. The exposed active layer 12 is corroded slightly with a tartaric acid group corrosive liquid, washed by water and dried. A substrate is mounted in a reaction chamber for a plasma CVD device, and a mixed gas of I vapor and Ar is introduced and pressure in the chamber is decompressed up to approximately 0.8Torr. Glow discharge is generated in the chamber, the substrate is exposed to plasma containing iodine ions for five min, the substrate is shifted to an electron-beam metallizing apparatus, thin-films 15, 16 in Al are formed, and a lift-off method is further executed, thus obtaining an MES.FET.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application: Industry The present invention relates to a method of forming a gate of a field effect transistor of an X-V group compound semiconductor.

Conventional configurations and their problems In recent years, in industry, mainly in the high frequency communication equipment industry,
- The field-effect transistor (hereinafter referred to as MES or FET) made of group compound semiconductors is a key device.
It is widely produced.

The ■-■ group compound semiconductor here refers to gallium arsenide (G
aAs) and indium phosphide (Ink).

Let me explain a little about MES/FET. ME in Figure 1
A perspective view of an S-FET is shown. 1 is an insulating or semi-insulating substrate, 2 is an active layer made of a 3-5 compound semiconductor, 3, 4
are the source and drain, and 6 is the gate. A depletion layer spreads in the active layer directly under the gate, and this spread is controlled by the gate voltage. This function controls the cross-sectional area of the current path in the active layer between the source and drain. This is the basic principle of MES-FET.

The term "semi-insulating" refers to a volume resistivity of 10Ω·m.

By the way, as can be seen from FIG. 1, MES-FICT is a silicon film in which the gate metal is formed in direct contact with the semiconductor active layer.
) utilizes key barriers. Therefore, the presence of inclusions between the metal and the semiconductor active layer causes a decrease in FKT characteristics, especially mutual conductance (Elm). One of these inclusions is generated during the manufacturing process of MES-FET.

It is well known that a semiconductor active layer has a surface oxidation layer.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a method for forming a gate that improves the mutual conductance (gm) of a MES-FET having an If-V compound semiconductor active layer.

Purchase version of the invention The method for forming gates of MES and FKT of the present invention includes a first step of exposing the surface of a Z-V group compound semiconductor to a plasma atmosphere containing iodine ions, and a step of depositing metal on the semiconductor surface by vapor deposition or sputtering. and a second step of forming a film, thereby improving the mutual conductance (&m) of MKS@FIT.

The present invention is particularly effective when the II-V compound semiconductor is gallium arsenide (GaAs).

In addition, the first step of exposing the surface of the I[-V group compound semiconductor to a plasma atmosphere containing iodine ions and the second step of forming a metal film on the semiconductor surface by vapor deposition or sputtering are the same. MES- gm of FET
This will further improve the

In addition, in the first step, the semiconductor is
If the temperature is maintained at 00°C, the effect of the present invention becomes even more remarkable.

The reason why treatment of iodine (I) ions on the semiconductor surface improves 9m of MES-FIT as described above is estimated as follows. That is, conventional MES
-The FET gate fabrication procedure involves exposing the semiconductor surface using an appropriate method, then lightly etching it with an etchant, washing it with water, and
After drying, transporting, etc., the semiconductor surface is exposed to the outside air, and then installed in a vapor deposition device or a sputtering device. Through operations such as washing with water and drying, the surface of the ■-■ group compound semiconductor is
It is well known that a natural oxide film of about 100% is formed. Therefore, it is presumed that in the conventional method, the gate metal film was formed on a naturally oxidized film that had changed to some extent. In carrying out the present invention, the semiconductor surface is ablated with iodine ions before the gate metal film is formed, and the gate metal is immediately formed, so that the natural oxide film on the semiconductor surface becomes relatively thin. Therefore, the mutual conductance of 1 m is improved.

Description of examples Examples of the present invention will be described below.

A substrate in which a GaAs active layer (approximately 20 mm thick) containing impurities and sulfur (S) at a concentration of approximately 2 x 1o''/cl is formed on semi-insulating gallium arsenide (CaAs) (1 in Figure 1) by vapor phase growth. prepared.

Next, a first GaAs active layer was formed on the substrate using a mixture of caustic soda (NaOH) aqueous solution and hydrogen peroxide.
Etch the mesa as shown. In the figure, the thickness of the GaAs active layer was about 2000.

Next, source and drain ohmic electrodes were formed as follows. Gold (Au)-germanium (Ge) alloy (
Ge (containing 12W%) is about 1300A, nickel (N1) is about 300AI, and gold (Au) is about 3
Source and drain electrode patterns were formed by sequential electron beam evaporation using a lift-off method, followed by heat treatment at 450° C. for 3 minutes in an argon (Ar) stream.

Next, a gate corresponding to 6 in FIG. 1 is formed. The gate electrode pattern was formed using a lift-off method. The procedure of gate formation according to the conventional method is shown in FIG. FIG. 2 is a sectional view of the structure near the gate. In the figure, 11 is a semi-insulating substrate, 12 is an active layer, and 13 is a chemical vapor deposition (chemical vapor deposition) used as a spacer in the lift-off method.
16.1e is a metal film formed by a vapor deposition method or a spunter method. The procedure is as follows.

First, on the active layer, a SiO film with a thickness of about 5000 nm was deposited on the substrate at 320°C using a DJ-83000VD device manufactured by Kokusai Denki Co., Ltd.
2 was formed, and then a positive resist manufactured by Tokyo Ohka Co., Ltd., 0
FPR-800 is applied ((a)).

Furthermore, the resist film is processed using the photophosphor method,
Furthermore, SiO2 is processed with a buffer solution consisting of a mixture of hydrofluoric acid and ammonium fluoride aqueous solution ((b)).

Next, the exposed active layer is slightly etched with a tartaric acid-based etchant, washed with water, and dried, after which a predetermined metal film is immediately formed by a vapor deposition method or a spunter method.

The thickness of this metal film is usually less than that of the spacer 5102 ((c)). Furthermore, the resist film is immersed in heated acetone to swell.

It is dissolved and removed together with the metal film on the resinite film ((d)). Thus, the MES-FET is completed.

In this example, aluminum (Aβ) was used as the metal material for the gate. Formation of A4 film is 1×1σ6 Torr
It was formed by the electron beam evaporation method in vacuum as described below. Said Ad
The film thickness of the film was approximately 4Q008.

In this example, in FIG. 1, the length I and the channel length were 1 μm and the channel width W was 250 μm. The conditions for measuring the mutual conductance (9m) are a drain voltage of 3V and a drain current of 35771A. A curve tracer was used for the 9m measurement.

A comparative example using the conventional method is shown in Lot No. 1 in Table 1. In this example, a plurality of gallium arsenide substrates are used in each of the rotors 1 to 1, and each substrate is equipped with several hundred MEs for measurement.
There is S-FIT. The transconductance values in Table 1 are average values across these FETs that indicate FET characteristics.

Next, an embodiment of the method for forming MES and FET transistors according to the present invention will be described with reference to FIG. FIG. 2 is a sectional view of the structure near the gate. The procedure is as follows.

First, on top of the semiconductor active layer,
-8300 at a substrate temperature of 320°C, a silicon dioxide (SiO2) film with a thickness of about 5000 is formed, and then a positive resist 0FPR-800 manufactured by Tokyo Ohka Co., Ltd. is applied (
(a) ). Further, the resist film is processed by the FoI-phosphorus method, and silicon oxide (SiOz) is further processed into buffer solution 1 consisting of a mixture of hydrofluoric acid and ammonium fluoride aqueous solution ((b)). Next, the exposed active layer is slightly etched with a tartaric acid-based etchant, washed with water, and dried.

Below is the blank space in Table 1, loft number 2, which will be made like fire after this. First, a substrate is placed in a reaction chamber of a plasma device, that is, a plasma/CVD device, and iodine (I) vapor and argon (Ar) are used.
) is introduced into the reaction chamber to bring the pressure inside the reaction chamber to about 0. Adjust to B Torr.

The outline of the plasma apparatus used is schematically shown in FIG. In Figure 3, zl is the chamber (reaction chamber)
, 22 is a semiconductor substrate, 23 is a table on which the substrate is placed, 1
4 is a heater, 215 is a thermocouple for temperature measurement, L6 is a glass container for generating iodine (I) vapor, '2-7 is a glass three-way valve, 28 is a glass valve, 'L9 is rubbed together, 3
0 is a mass of iodine (I), and 31 is for heating the iodine.To introduce a mixed gas of iodine (I) and argon (Ar) into the mantle reaction chamber, a heater 24 is used to heat the iodine (I) mixture gas. is introduced into the chamber through the three-way valve 27.

Next, a glow discharge is caused in the chamber 11 with a high frequency input of 50 W at 13.56 MHz. The substrate is then exposed to plasma containing iodine ions for 5 minutes.

Next, immediately transfer the substrate to an electron beam evaporator,
A thin aluminum (AC) film having a thickness of 400.8 mm is formed (FIG. 2(C)). Furthermore, MyLS-FET is obtained by performing the lift-off method as described above ((d)
').

This MES, FET is considerably better in terms of gm than the comparative example.

In addition, lot numbers 3 to 9 in Table 1 are related to the present invention, in which the semiconductor active layer is exposed to plasma containing iodine (1) ions and the gate metal film is formed in the same chamber. An example will be shown which is carried out promptly in order. An outline of this device is shown in FIG. ~This device is basically an electron beam evaporation device, which has been modified. +1 is a chamber (reaction chamber), 12 is a semiconductor substrate, 3 is a substrate holder, 44 is a heater, +6 is a thermocouple, 46 is an aluminum source, 7 is a guide for guiding gas containing iodine vapor, 4
8 is a glass container for generating iodine vapor, +9 is a glass three-way valve, is a glass valve, 1 is a sliding joint, 2 is an iodine (I) lump, 11, 3 is a vessel for heating the iodine. The mantle heater, approximately 4, is an electrode made of tungsten wire for glow discharge. The method for introducing the mixed gas of iodine (I) vapor and argon (Ar) into the reaction chamber is as described above.

First, a semiconductor substrate having an active layer lightly etched with a tartaric oxygen etchant is placed in the apparatus shown in FIG.

Next, if necessary, the temperature is raised to a predetermined temperature by the heater 44 and maintained at that temperature.

Next, a mixed gas of iodine (I) vapor and argon (Ar) is introduced into the chamber 41 while adjusting the degree of vacuum to about 0.5 Torr. This adjustment is done using a three-way valve with a 9V
It is done by c. A 600VA Nemen transformer causes a glow discharge in chamber 41, and then! Maintain for a specified period of time. After that, immediately apply a high vacuum using a diffusion pump, etc., and pull within 1X
When the degree of vacuum in the chamber 41 reaches 10-6 Torr or less, an electron beam is applied to the aluminum (A4) sheet to perform aluminum (Al) vapor deposition.

The subsequent process is as described above. Thus, MES-
FIT was obtained.

7. The method of forming a gate metal film after exposing a semiconductor active layer to plasma containing iodine (I) ions has a higher transconductance than the conventional method. (,!i'm).

Also, when comparing lot numbers 2 and 3 to 9 in Table 1,
When the semiconductor active layer is exposed to the outside air between the first step of exposing the semiconductor active layer to plasma containing iodine (I) ions and the second step of forming the gate metal film, the resulting MES-FET GM Gaya! It can be seen that it deteriorates.

Further, a more preferable treatment time for plasma treatment is 2 minutes to
It turns out that it takes about 15 minutes. Further, it is found that the most preferable substrate temperature for plasma processing is 7o to 100°C.

Until now, aluminum (Al
), but the present invention is not limited to this, and similar results were obtained when other metals were used for the gate. Further, although only gallium arsenide (GaAs) has been described, the effects of the present invention were also exhibited in indium phosphide MES/FETs.

Effects of the Invention As is clear from the above explanation, the present invention has the advantage of exposing the semiconductor surface to a 7° plasma atmosphere containing iodine (I) ions
and a second step of depositing a metal on the surface of the semiconductor by a vapor deposition method or a Nubatter method] I[-V compound semiconductor MES-FET gate formation method Thus, the mutual conductance (,!9
MES-FET with large m) can be obtained.

Furthermore, after the above step, a method for forming a gate of an MES/FET of a group I[-V compound semiconductor is provided, by directly performing a second step without exposing the surface of the semiconductor to the outside air. Thus, a MES-FET with even higher gm can be obtained.

Further, in the first step, the semiconductor is heated to a temperature of 70 to 1o.

When kept at 0.degree. C., the resulting MES-FETOgm is further improved.

[Brief explanation of the drawing]

Figure 1 is a perspective view of a field effect transistor, Figure 2 (
a) to (d) are cross-sectional views showing the process of gate formation in the method of the present invention, FIG. 3 is a configuration diagram of a plasma apparatus for implementing the method of the present invention, and FIG. FIG. 2 is a configuration diagram of an apparatus in which processing and electrode formation are performed in the same reaction chamber. 1... Insulating or semi-insulating substrate, 2...
・Semiconductor active layer, 3, 4... Source and drain, 6... Gate, 11... Insulating or semi-insulating substrate, 12... Semiconductor active layer, 13.
...Chemical vapor deposition (CVN) silicon dioxide, 14...
...Resist film, 15.16...Metal film, 2
1...Chamber, 22...Semiconductor substrate, 23...Cheagle for mounting the substrate, 24...
... Heater, 25 ... Thermocouple, 26 ...
...Glass container for generating iodine vapor, 27
...Three-way valve, 28...Two-way valve, 29.
...Grinding together, 30...Iodine lump, 3
1... Mantle heater, 41...
Chamber, 42...Semiconductor substrate, 43...
...Substrate holder, 44...Heater, 46
・・・Thermocouple, 46・・・Aluminum・
Source, 4A...Teflon guide for guiding the mixed gas containing iodine, 48...Glass container for generating iodine vapor, 49...Three-way valve , 50... Two-way valve, 51... Grinding, 52... Iodine ring, 53... Mantle book heater, 54... Tungsten wire electrode for glow discharge reservoir. Name of agent: Patent attorney Toshio Nakao and 1 other person3 Figure 1 Figure 2, Figure 3 Figure 4

Claims (4)

[Claims] (1) A field-effect type comprising a first step of exposing the surface of a III-V semiconductor to a plasma atmosphere containing iodine ions, and a second step of forming a metal film on the semiconductor surface by vapor deposition or sputtering. How to form a transistor gate. (2) After the first step, the second step is performed without exposing the semiconductor surface to the outside air. Formation method. (3) A method for forming a gate of a field effect transistor according to claim 1, wherein the N-V group compound semiconductor is potassium arsenide. (4) A method for forming a gate of a field effect transistor according to claim 1, characterized in that in the first step, the semiconductor is maintained at a temperature of 70 to 100°C.