JPS58114463A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPS58114463A JPS58114463A JP21359081A JP21359081A JPS58114463A JP S58114463 A JPS58114463 A JP S58114463A JP 21359081 A JP21359081 A JP 21359081A JP 21359081 A JP21359081 A JP 21359081A JP S58114463 A JPS58114463 A JP S58114463A
- Authority
- JP
- Japan
- Prior art keywords
- film
- compound semiconductor
- semiconductor device
- ions
- stream
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 150000001875 compounds Chemical class 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000001257 hydrogen Substances 0.000 claims description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 11
- 230000001681 protective effect Effects 0.000 claims description 9
- -1 hydrogen ions Chemical class 0.000 claims description 4
- 150000003377 silicon compounds Chemical class 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 10
- 230000002411 adverse Effects 0.000 abstract description 3
- 229910020776 SixNy Inorganic materials 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 2
- 229910017401 Au—Ge Inorganic materials 0.000 abstract 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 abstract 1
- 229910000070 arsenic hydride Inorganic materials 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 15
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 101100215641 Aeromonas salmonicida ash3 gene Proteins 0.000 description 1
- 101100071193 Aeromonas salmonicida ash4 gene Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 229920006226 ethylene-acrylic acid Polymers 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
ａ）発明の技術分野
本発明は化合物半導体装置の製造方法に係り、特にその
表面を被覆する保護絶縁膜の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION a) Technical Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a method for forming a protective insulating film covering the surface of the device.
（２）従来技術と問題点
一般に、半導体素子の表面は外気からの水分の侵入を防
止し、又ゴミや塵などの付着を防ぐために、保護絶縁膜
が被覆され、場合によってはその被覆性を強くするため
、中性気流中で熱処理がなされる。このような保護絶縁
膜としては、シリコン化合物膜例えば酸化シリコン膜あ
るいは窒化シリコン膜が汎〈用いられており、それはこ
れらの酸化膜あるいは窒化膜がその性質を良く解明され
ていて、また形成法も確立されているためである・しか
しながら、シリコン半導体素子では同材質の化合物であ
るため、問題は余シ起らないが、ガリウム砒素（ＧａＡ
Ｓ）などの化合物半導体には甚だ不都合な問題が生じる
。例えば第１図はＧａＡＳショットキバリヤゲートグー
界効果トランジスタ（ＭＥＳＦＥＴ ”）の断面構造を
示しており、周波数ＩＭＨ２以上のマイクロ波帯能動素
子として知られているが、その表面に膜厚ｌ約５０００
人ｌの酸化シリコン膜ｌを被覆するう図において、２は
ＧａＡＳ基板、８はｎ型ｅａＡｓ動作層、会は金ゲルマ
ニウム（Ａｕ−Ｇｅ）からなるソース及びドレイン電極
、５はアルミニウム（ＡＪ）からなるゲート電極で、上
記酸化シリコン膜ｌはこれらの電極も形成された後に、
化学気相成長（ＣＶＤ）法又はヌバツタ法で被着する。(2) Prior art and problems In general, the surface of a semiconductor element is coated with a protective insulating film to prevent moisture from entering from the outside air and from adhering to dirt and dust. To strengthen it, it is heat treated in a neutral air stream. As such a protective insulating film, a silicon compound film such as a silicon oxide film or a silicon nitride film is widely used. However, since silicon semiconductor devices are made of the same material, no problems occur; however, gallium arsenide (GaA)
Compound semiconductors such as S) pose serious problems. For example, Figure 1 shows the cross-sectional structure of a GaAS Schottky barrier gate field effect transistor (MESFET), which is known as a microwave band active device with a frequency of IMH2 or higher.
In the figure, 2 is a GaAS substrate, 8 is an n-type EAAs active layer, 2 is a source and drain electrode made of gold germanium (Au-Ge), and 5 is made of aluminum (AJ). After these electrodes are also formed, the silicon oxide film l is
It is deposited by chemical vapor deposition (CVD) or the Nubatsuta method.
しかし、この酸化シリコン膜の被覆工程の良否によって
、トランジスタ特性の劣化、特にゲイン低下やノイズ増
加が見られ、それを検討したところその原因はＧａＡＳ
動作層と酸化シリコン膜との界面に存在する相互拡散層
にあると考えられる。However, depending on the quality of this silicon oxide film coating process, deterioration of transistor characteristics, especially gain reduction and noise increase, was observed, and when we investigated this, we found that the cause was GaAS.
This is thought to be due to the interdiffusion layer existing at the interface between the active layer and the silicon oxide film.
即ち、酸化シリコン膜はＣＶＤ法又はスパッタ法で被着
されるが、ＧａＡｓ基板は数１００℃に加熱して被着す
るから、その界面に相互拡散層が発生する。被着後、熱
処理すれば尚更、この層が画然とすることは言うまでも
ない。That is, the silicon oxide film is deposited by CVD or sputtering, but since the GaAs substrate is deposited by heating to several hundred degrees Celsius, an interdiffusion layer is generated at the interface. Needless to say, this layer becomes even more distinct if it is heat treated after deposition.
第２図はその相互拡散層を示す原子濃度凹表で、酸化シ
リコン膜をアルゴンイオンでスパッタ食刻しなからオー
ジェ電子分光法で分析した結果を（財）示しており、そ
の層幅は約１００人であろうまた、被着した酸化シリコ
ン膜は二酸化シリコン（ＳｉＯ２）のみではなく、分析
結果では５ｉＯｘ（Ｘ＜２）構造であることが判かり、
これは縁者間で良く知られている通りである。しかも、
５ｊ−Ｏｘは一定ではなくて、Ｇ ８Ａ Ｓ活性層に近
い程Ｓ１が過剰となっており、Ｓｉのダングリングボン
ド（ｄａｎｇｌｉｎｇｂｏｎｄ、）が出来ていると予想
され、これがキャリヤ捕獲中心をなして、ＧａＡｓ表層
の電子をトラップし、表層に表面空乏層が生じて、これ
が悪影響を与えていると推定される。Figure 2 is an atomic concentration concave table showing the interdiffusion layer, and shows the results of analysis using Auger electron spectroscopy after sputter etching a silicon oxide film with argon ions, and the layer width is approximately In addition, the deposited silicon oxide film was not only silicon dioxide (SiO2), but the analysis results showed that it had a 5iOx (X<2) structure.
This is well known among relatives. Moreover,
5j-Ox is not constant, and the closer to the G 8A S active layer, the more S1 becomes excessive, and it is expected that dangling bonds of Si are formed, and this forms the center of carrier capture, It is presumed that electrons in the GaAs surface layer are trapped and a surface depletion layer is generated in the surface layer, which has an adverse effect.
又、第２図に示すように、相互拡散１内ではＧａとＡ６
とが同量ではな（、Ａｓが過剰となっており、そうする
とＡｓ結合ができて金属Ａｓとなり、これにより酸化シ
リコン膜とＧａＡ、Ｅｌとの界面にリーク電流が流れ、
ｔ）！ Ｅ Ｓ Ｆ Ｅ Ｔ ’Ｊ性を劣化していると
予想される。Moreover, as shown in FIG. 2, within the mutual diffusion 1, Ga and A6
are not the same amount (, As is in excess, and then As bonds are formed to form metal As, which causes leakage current to flow at the interface between the silicon oxide film and GaA and El.
t)! It is expected that the E S F E T 'J property will be deteriorated.
（３）発明の目的
本発明はこのような電気待惚劣化の原因を取り除いて、
半導体装置の特性を改着することを目的とするものであ
る。(3) Purpose of the invention The present invention eliminates the causes of such electrical deterioration,
The purpose is to modify the characteristics of semiconductor devices.
（４）発明の構成
その目的は、半導体素子表面にシリコン化合物からなる
保護絶縁膜を被覆した後、保護絶ｔＭ中に水素イオンを
注入して、水垢気流中で熱処理する工程を含む製造方法
によって達成される。(4) Structure of the invention The purpose is to use a manufacturing method that includes the steps of coating the surface of a semiconductor element with a protective insulating film made of a silicon compound, implanting hydrogen ions in a protective tM, and heat-treating it in a limescale air stream. achieved.
（５）発明の実施例
本発明を、第１図に示すＧａＡｓ ＭＥＳＦＫＴＫ適用
する冥施例で説明すると、ｎ型ＧａＡ３活性層８をエピ
タキシャル成長した後、ソース及びドレイン電極傷とし
て、Ａｕ−Ｇｅを被着し、パターンユングし、次にｎ型
ＧａＡＳ活性層８のゲート電極下をエツチングしてリセ
ス構造（スイッチ速度が速くなる）にする。その上にＡ
Ｉからなるゲート電極５を被着形成し、次にＣＶＤ法で
膜厚ｌ約５０００ムシのＳｉＯｘ膜ｌを保護膜として表
面に被着する。(5) Embodiments of the Invention The present invention will be explained using an example in which GaAs MESFKTK is applied as shown in FIG. The n-type GaAS active layer 8 is then etched under the gate electrode to form a recessed structure (which increases the switching speed). A on top of that
A gate electrode 5 made of I is deposited and then a SiOx film l having a thickness l of about 5000 mm is deposited on the surface as a protective film by CVD.
゛ これら工程は公知の方法で行なわれるが、次いでイ
オン注入法によって水素イオンを５ｘｏｘ膜中に注入す
る。そのドーズ量は１０／ａｉｌ程度にし、次に水素ガ
ス気流中で４００℃に加熱し、約２０分間熱処理する。``These steps are performed by known methods, and then hydrogen ions are implanted into the 5xox film by an ion implantation method. The dose is set to about 10/ail, and then heated to 400° C. in a hydrogen gas stream for about 20 minutes.
その後に、Ｓｉ○Ｘ膜１ｔ−窓あけして、グー鼾、ソー
ス及びドレイン電極配線（図示していない）を形成する
が、これらの電極配線はイオン注入と熱処理との水素処
理後に行なってもよい。After that, a window is opened in the Si○X film, and source and drain electrode wiring (not shown) is formed, but even if these electrode wiring are done after the hydrogen treatment of ion implantation and heat treatment, good.
かような水素処理を加えることによって、半導体素子の
電気的特性は改善され、代表例として、第８口軽）、（
６）に相互コンダクタンス（ｇｍ）の周波数に対するデ
ーメト１表を示している６第３区（ａ）は水素処理工程
のない場合のデータ、第３図中）は水素処理を加えたデ
ータである。図のように、水素処理のない場合は周波数
２ｏｏｐｚ以上となるとｇｍが低下しているが、水素処
理すれば高周波に２けるｇｍの低下がなく、ｇｍの周波
数分散が解消される。第８口軽）は２００Ｈ２近傍に変
曲点があるが、この周波数はＧａＡ、３活性層の表面処
理によって前後し、一定しない。しかし、何れにしろ水
素処理はｇｍを向上し、ゲイン特性を改善するものであ
る。By applying such hydrogen treatment, the electrical characteristics of semiconductor devices are improved.
6) shows the Demet 1 table of mutual conductance (gm) versus frequency. 6 Section 3 (a) is the data without the hydrogen treatment process, and Figure 3) is the data with the hydrogen treatment added. As shown in the figure, without hydrogen treatment, gm decreases when the frequency exceeds 2 oopz, but with hydrogen treatment, there is no decrease in gm at high frequencies, and the frequency dispersion of gm is eliminated. The 8th round) has an inflection point near 200H2, but this frequency fluctuates depending on the surface treatment of the GaA and 3 active layers and is not constant. However, in any case, hydrogen treatment increases gm and improves gain characteristics.
これは多量の水パが存在す終ば、水素が金属Ａｓと反応
して例えばＡＳＨ３あるいはＡＳＨ４などとなって揮発
し、同時に過剰の８１と水素とは原子結合してダングリ
ングボンドをなくする効果があるためと考えられ、した
がって相互拡散層の悪影響が除去される。This is due to the effect that when a large amount of water is present, hydrogen reacts with metal As, forming ASH3 or ASH4 and volatilizing, and at the same time, excess 81 and hydrogen form atomic bonds, eliminating dangling bonds. This is thought to be due to the fact that the interdiffusion layer has an adverse effect on the interdiffusion layer.
（６）発明の効果
以上はＧａＡｓＭＥＳＦＥＴ ｔ＄施例として説明した
が、本発明はその他のＩ−Ｖ族化合物あるいは１−Ｍ族
化合物などの化合物半導体装置に適用して、同様の効果
があるものである。(6) Effects of the invention Although the above description has been made using a GaAs MESFET t$ example, the present invention can be applied to other compound semiconductor devices such as IV group compounds or 1-M group compounds, and similar effects can be obtained. It is.
また、上記実施例は酸化シリコン膜で説明したが、シリ
コン化合物からなる保護絶鞭粛として窒化シリコン膜が
あり、これもＳｉｘＮｙ 構造であり、このような窒
化シリコン膜にも応用して同じ好結果かえられることは
当然である。In addition, although the above embodiment was explained using a silicon oxide film, there is a silicon nitride film as a protective film made of a silicon compound, which also has a SixNy structure, and the same good results can be obtained by applying it to such a silicon nitride film. It is natural that they will be changed.
したがって、本発明は化合物半導体装置の電気的特性、
特に出力特性や雑音などの改善に役立つすぐれたもので
ある、Therefore, the present invention provides electrical characteristics of a compound semiconductor device,
It is especially useful for improving output characteristics and noise.
第１図はＧａＡｓＭＥＳＦＥＴの断面構造図、第２図は
相互拡散層の原子濃度図表、第３図は水素処理有無のＧ
ｍ特性図表であるう図中、１は酸化シリコン膜、２はＧ
ａＡＳ基板、８はＧａＡＳ活性層、４はソース及びドレ
イン電極、５はゲート電極を示す。
第１図Figure 1 is a cross-sectional structure diagram of a GaAs MESFET, Figure 2 is an atomic concentration diagram of the interdiffusion layer, and Figure 3 is a graph of G with and without hydrogen treatment.
In the figure, 1 is a silicon oxide film, 2 is a G
The aAS substrate, 8 is a GaAS active layer, 4 is a source and drain electrode, and 5 is a gate electrode. Figure 1
Claims (1)
被覆し、次に該保護絶縁膜中に水素イオンを注入して、
水素気流中で熱処理する工程が含まれてなることを特徴
とする化合物半導体装置の製造方法。Covering the surface of the semiconductor element with a protective insulating film made of a silicon compound, then implanting hydrogen ions into the protective insulating film,
A method for manufacturing a compound semiconductor device, comprising a step of heat treatment in a hydrogen stream.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21359081A JPS58114463A (en) | 1981-12-26 | 1981-12-26 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21359081A JPS58114463A (en) | 1981-12-26 | 1981-12-26 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58114463A true JPS58114463A (en) | 1983-07-07 |
Family
ID=16641712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21359081A Pending JPS58114463A (en) | 1981-12-26 | 1981-12-26 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58114463A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0152624A2 (en) * | 1983-12-24 | 1985-08-28 | Sony Corporation | Method of manufacturing a semiconductor device having a polycristalline silicon-active region. |
| JPS63104483A (en) * | 1986-10-22 | 1988-05-09 | Mitsubishi Electric Corp | Semiconductor device |
-
1981
- 1981-12-26 JP JP21359081A patent/JPS58114463A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0152624A2 (en) * | 1983-12-24 | 1985-08-28 | Sony Corporation | Method of manufacturing a semiconductor device having a polycristalline silicon-active region. |
| JPS63104483A (en) * | 1986-10-22 | 1988-05-09 | Mitsubishi Electric Corp | Semiconductor device |
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