JPS60245180A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60245180A JPS60245180A JP10102684A JP10102684A JPS60245180A JP S60245180 A JPS60245180 A JP S60245180A JP 10102684 A JP10102684 A JP 10102684A JP 10102684 A JP10102684 A JP 10102684A JP S60245180 A JPS60245180 A JP S60245180A
- Authority
- JP
- Japan
- Prior art keywords
- forming
- active layer
- layer
- semiconductor
- shaped groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の製造方法に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a method for manufacturing a semiconductor device.
従来例の構成とその問題点
従来、半導体装置（以下ＩＦＦＴと略す）を作製する場
合、ソース、ドレインのオーミック層およびゲートの活
性層は、２回のイオン注入技術により行なっている。こ
の従来の方法では、活性層とオーミック層の濃度差が大
きく、イオン注入技術により注入された注入イオンを活
性化するために行なう高温熱処理により、不純物の横方
向拡散が起こり、ＦＩＣＴの閾値電圧が±ｏ、ｏ ｅ
ｖバラつき、また歩留りも３０チ程度であり問題となる
。Conventional Structure and Problems Conventionally, when manufacturing a semiconductor device (hereinafter abbreviated as IFFT), the ohmic layers of the source and drain and the active layer of the gate are formed by two ion implantation techniques. In this conventional method, the concentration difference between the active layer and the ohmic layer is large, and the high-temperature heat treatment performed to activate the implanted ions using ion implantation technology causes lateral diffusion of impurities, which increases the threshold voltage of the FICT. ±o, o e
V variation and the yield are also about 30 inches, which is a problem.
発明の目的
本発明の目的は、注入後の不純物の横方向拡散による閾
値電圧のバラつきの小さな半導体装置の製造方法を提供
することにある。OBJECTS OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a semiconductor device with small variations in threshold voltage due to lateral diffusion of impurities after implantation.
発明の構成
本発明の半導体装置の製造方法は、半導体基板の一主面
に、−導電型の半導体層を形成する工程と、前記半導体
層の厚みを横切って、前記半導体基板の表面にＶ形の溝
を形成する工程と、前記半導体基板を熱処理して前記Ｖ
形の溝の底部に前記半導体層と同一導電型で不純物濃度
の低い活性層を形成する工程と、前記活性層にゲート電
極を、前記活性層の左右の前記半導体層にそれぞれソー
スミ極、ドレイン電極を形成する工程とで構成される。Structure of the Invention The method for manufacturing a semiconductor device of the present invention includes the steps of forming a - conductivity type semiconductor layer on one main surface of a semiconductor substrate, and forming a V-shaped semiconductor layer on the surface of the semiconductor substrate across the thickness of the semiconductor layer. a step of forming a groove of V; and a step of heat treating the semiconductor substrate to form a groove of V.
forming an active layer with the same conductivity type as the semiconductor layer and low impurity concentration at the bottom of the shaped groove; forming a gate electrode on the active layer; and forming a source electrode and a drain electrode on the semiconductor layers on the left and right sides of the active layer, respectively. It consists of a step of forming a.
実施例の説明 以下本発明を実施例に基づき詳細に説明する。Description of examples The present invention will be described in detail below based on examples.
第１図は、本発明の一実施例を示す製造工程図である。FIG. 1 is a manufacturing process diagram showing an embodiment of the present invention.
第１図ａにおいて、Ｇａｐｓ半絶縁性基板１０表面にシ
リコンをイオン注入（１５０ＫｅＶ 、 １×１ｄｔｙ
２）し、イオン注入層２を形成する。その後、ｃｖｎに
よりシリコン窒化膜３を堆積させ、ホトエツチング技術
により、グレーティングのための窓４をあける。ＨＮＯ
３： ＨＣｌ−１：４のエツチング液により、第１図す
に示すようにＶ形の溝６を形成する。この時イオン注入
層２の厚さが１μｍであれば１μｍ以上のエツチング溝
６の形成が必要である。In FIG. 1a, silicon is ion-implanted (150 KeV, 1×1 dty) onto the surface of the Gaps semi-insulating substrate 10.
2) Then, an ion implantation layer 2 is formed. Thereafter, a silicon nitride film 3 is deposited by CVN, and windows 4 for gratings are opened by photoetching. HNO
3: Form a V-shaped groove 6 as shown in FIG. 1 using an etching solution of HCl-1:4. At this time, if the thickness of the ion implantation layer 2 is 1 .mu.m, it is necessary to form the etching groove 6 of 1 .mu.m or more.
Ｖ溝部の形成のためのエツチング後、第１図Ｃに示すよ
うに、ムＳ圧下でｓ６ｏ’ｃ、４ｏ分間、熱処理を行な
い、Ｖ溝部０片部のＧａＡｓの解離成長により活性層６
を形成する。After etching to form the V-groove, as shown in FIG.
form.
その後、シリコン窒化膜２を除去し、新たに、シリコン
窒化膜７を堆積させ、従来のホトエツチング技術と蒸着
技術により、オーミック電極であるソース電極８．ドレ
イン電極９を、ショットキ電極であるゲート電極１０を
形成する。前記製造工程により半導体装置（ＦＥＴ）が
得られる。Thereafter, the silicon nitride film 2 is removed, a new silicon nitride film 7 is deposited, and a source electrode 8, which is an ohmic electrode, is etched using conventional photoetching and vapor deposition techniques. A drain electrode 9 and a gate electrode 10 which is a Schottky electrode are formed. A semiconductor device (FET) is obtained through the manufacturing process.
次にＶ溝部に形成される活性層の不純物濃度について説
明する。Next, the impurity concentration of the active layer formed in the V groove will be explained.
第２図は、ソース・ドレインの注入層の不純物濃度と熱
処理によって形成される溝部のゲートの活性層の不純物
濃度の関係を示す。FIG. 2 shows the relationship between the impurity concentration of the source/drain injection layer and the impurity concentration of the active layer of the gate in the trench formed by heat treatment.
活性層６は熱処理によって、溝片部のＧａＡｓが解離し
、溝底部に溜まるような形で形成され、イオン注入のド
ーズ量が１×１０１４ｃｍ−２のとき、ソース・ドレイ
ンのオーミック層の不純物濃度は、Ｉ Ｘ １０１８Ｃ
ｍ ” 、活性層６の不純物濃度は５Ｘ１０′６ｃｍ
’程度となる。The active layer 6 is formed by heat treatment in such a way that GaAs in the groove pieces dissociates and accumulates at the bottom of the groove, and when the ion implantation dose is 1 x 1014 cm-2, the impurity concentration of the source/drain ohmic layer decreases. is IX1018C
m”, the impurity concentration of the active layer 6 is 5×10′6 cm
'It will be about.
本発明の製造工程により、１ウエハー内のＦＩＣＴの閾
値電圧のバラつきは均一な不純物濃度の活性層形成によ
り±ｏ、ｏａｖとな９従来の半分程度に減少し、歩留り
も不純物の横方向拡散が制御されるため１ｏチ程度向上
し４０チとなった。Through the manufacturing process of the present invention, the variation in threshold voltage of FICT within one wafer is reduced to ±o, oav9 by forming an active layer with a uniform impurity concentration, and is reduced to about half that of the conventional method. Because of the control, it improved by about 1 inch to 40 inches.
なお、半導体絶縁基板はＧａＡｓに限らず、Ｓｉ。Note that the semiconductor insulating substrate is not limited to GaAs, but may also be Si.
ＩｎＰ ＺｎＳなどでもよく、絶縁膜もシリコン窒化膜
に限らず、シリコン酸化膜など、本発明の製造工程の高
温熱処理に耐えうる膜であればよい。壕だ第１図に示し
た実施例では（ｒａＡｓ半絶縁性基板の表面にイオン注
入により半導体層を形成したが、液相エピタキシャルあ
るいは分子線エピタキシャルナトのエピタキシャル法を
用いて形成しても良い。InP, ZnS, etc. may be used, and the insulating film is not limited to a silicon nitride film, but may be any film that can withstand the high temperature heat treatment in the manufacturing process of the present invention, such as a silicon oxide film. In the embodiment shown in FIG. 1, the semiconductor layer was formed on the surface of the raAs semi-insulating substrate by ion implantation, but it may also be formed using liquid phase epitaxial or molecular beam epitaxial methods.
発明の効果
本発明により、１回のイオン注入および基板表面上のＶ
溝形成のエツチング工程、更に熱処理工程のみで活性層
を形成し、閾値電圧のバラつきを従来の半分以下に抑え
、歩留りも向上できた。このことにより、本発明は半導
体装置の製造方法において、有効であることがわかる。Effects of the Invention According to the present invention, one ion implantation and V
By forming the active layer using only the etching process for forming grooves and the heat treatment process, we were able to suppress variations in threshold voltage to less than half of the conventional level and improve yield. This shows that the present invention is effective in the method of manufacturing a semiconductor device.
第１図（ａ）〜（ｄｌは本発明の一実施例のＦＥＴ０製
造工程図、第２図はオーミック層不純物濃度と活性層不
純物濃度の関係を示す図である。
１・°°゛・ＧａＡｓ半絶縁性基板、２・・・・・オー
ミ、り層（ソース・ドレイン）、３．７・・・・・・シ
リコン窒化膜、４・・・・・活性層用エツチング窓、５
・・・・・・■溝、６・・・・・・活性層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図
（Ｃ詐ｔ−３）
８
０
驕
電
ト
Ω１６
ＩＩＩ２Ｉｌθ
枦
執
０FIGS. 1(a) to (dl) are FET0 manufacturing process diagrams according to an embodiment of the present invention, and FIG. 2 is a diagram showing the relationship between the ohmic layer impurity concentration and the active layer impurity concentration. 1.°°゛.GaAs Semi-insulating substrate, 2... Ohmic layer (source/drain), 3.7... Silicon nitride film, 4... Etching window for active layer, 5
...... ■Groove, 6... Active layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 (C deception t-3) 8 0 Edento Ω16 III2Ilθ 枦士0
Claims (1)
工程と、前記半導体層の厚みを横切って前記半導体基板
の表面にＶ形の溝を形成する工程と、前記半導体基板を
熱処理して、前記Ｖ形の溝の底部に前記半導体層と同一
導電型で不純物濃度の低い活性層を形成する工程と、前
記活性層にゲート電極を、前記活性層の左右の前記半導
体層にそれぞれソース電極、ドレイン電極を形成する工
程を含むことを特徴とする半導体装置の製造方法。forming a − conductivity type semiconductor layer on one principal surface of the semiconductor substrate; forming a V-shaped groove on the surface of the semiconductor substrate across the thickness of the semiconductor layer; and heat-treating the semiconductor substrate. forming an active layer of the same conductivity type and low impurity concentration as the semiconductor layer at the bottom of the V-shaped groove; forming a gate electrode on the active layer; and forming a source on the semiconductor layers on the left and right sides of the active layer. A method for manufacturing a semiconductor device, comprising a step of forming an electrode and a drain electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10102684A JPS60245180A (en) | 1984-05-18 | 1984-05-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10102684A JPS60245180A (en) | 1984-05-18 | 1984-05-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60245180A true JPS60245180A (en) | 1985-12-04 |
Family
ID=14289677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10102684A Pending JPS60245180A (en) | 1984-05-18 | 1984-05-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60245180A (en) |
-
1984
- 1984-05-18 JP JP10102684A patent/JPS60245180A/en active Pending
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