JPS61290714A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the thermal strain produced in a semiconductor substrate due to a difference in thermal expansion coefficient between the substrate and a covering film provided for preventing the scattering of an impurity and to improve the yield of the product, by performing a heat treatment after forming the covering film on the substrate and removing a part of the covering film. CONSTITUTION:Ions of a donor impurity Si 6 are selectively implanted in one principal surface of a GaAs substrate 1. A covering film 7 of phosphorus or silicon oxide glass is then formed for preventing the scattering of the As. The portions of the film 7 not included in the regions where elements are to be formed (the film portions for separating the substrate) are removed both in the vertical and transverse directions, so that groves 9 are provided in those directions. The substrate 1 is thereafter heated and annealed to diffuse the Si, whereby N-type active layers 2 and N<+> type diffused layers 3 for source and drain regions are formed. Consequently, any thermal strain caused by a difference in thermal expansion coefficient between the substrate 1 and the covering film 7 is absorbed by the grooves 9. Therefore, no strain is produced during the heat treatment and the yield of the products can be improved.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to compound semiconductor devices, particularly GaAs (gallium
Arsenic) FET (@field effect transistor) manufacturing technology.

[Background technology]

Regarding PET, which is a basic element constituting a GaAs IC, MESFET (Schottky 11-wall FET) has become the mainstream and development is progressing.

The steps for manufacturing this MBSFET will be explained with reference to the completed cross-sectional view of the MBSFET shown in FIG. A type scattering layer 3 is formed, an n-type active layer 2 is formed therebetween, and source/drain electrodes 4 made of metal (for example, AuQe) are provided for ohmic connection to the n++ layer 3. A gate metal 5 made of a metal (for example, 0) that forms a Schottky barrier is provided on the n-type active layer 2 sandwiched between
E 8 FET is a three-terminal device, and by changing the gate voltage Vg with voltage VdS applied between the drain and source, the depletion layer under the gate electrode is controlled, and the on/off operation of the source-drain current is controlled. It is possible to switch between (Published by Kogyo Kenkyukai, [Electronic Materials J, August 1984 issue, P34-P40) In the present applicant, K for forming an n-type active layer on a GaAs substrate is a wafer-shaped GaAs substrate 1 as shown in FIG. After implanting ions of donor impurities such as Si and 3e into one main surface, a phosphorus-silicon oxide glass such as phosphorus silicate glass (hereinafter referred to as PSG) is deposited on the main surface of the substrate having the ion-implanted impurities 6. A method of performing activation annealing (700 to 800° C., 20 minutes) with a coating 7 made of silicon nitride (hereinafter referred to as S) or silicon nitride (hereinafter referred to as S) is being considered. The reason for providing such a coating 7 is that during annealing, As in the GaAs in the GaAs substrate 1 is dissipated, the proportion of Ga component in the substrate increases, and the electron mobility in the semiconductor decreases. This is to prevent this from happening.

However, research by the present inventors has clearly shown that distortion occurs due to a large difference in the thermal expansion coefficient of the PSG or 8i3N coated with respect to the QaS substrate. That is, the surface of a GaAs substrate coated with a film such as PSG, st, N, etc., has its thermal expansion restricted to one side during annealing and is curved as shown by the arrow in FIG. 8, resulting in distortion of the wafer. Ion-implanted impurities are trapped in strained areas and activation is incomplete, resulting in partial deterioration of electronic performance characteristics, resulting in variations in the characteristics of semiconductor devices manufactured from this wafer. I know you'll be busy.

[Purpose of the invention]

The present invention has been made to overcome the above-mentioned problems.

The purpose of the present invention is to prevent the occurrence of thermal distortion during activation processing of GaAs substrates and to improve the yield of semiconductor products.
be.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in manufacturing a GaAs semiconductor device, after impurity ions are implanted into one main surface of a wafer-shaped GaAs substrate to form an active layer, PSG or the like is implanted onto the main surface to prevent the impurities from escaping. After forming a film and removing the film on the vertical and horizontal scribe lines, a heat treatment is performed to activate the impurity ion implantation layer, which reduces thermal expansion with the film. This eliminates thermal distortion of the substrate due to coefficient differences and improves product yield.

Embodiment C] FIGS. 1 to 5 show an embodiment of the present invention, and are cross-sectional views of a process mainly for forming an n-type active layer of a GaAs semiconductor device. FIG. 6 is a plan view of the entire wafer corresponding to the process shown in FIG. 3. Each step will be explained below.

(1) A semi-insulating GaAs substrate (wafer) 1 is prepared, and a predetermined amount of donor impurity Si is ion-implanted into the main surface of the substrate using a photoresist mask a to form an element formation region, that is, an electrode. A Si ion implantation layer 6 for an ohmic contact layer and an active layer is formed. (Fig. 1) (2) Next, PS is applied to the surface of the substrate 1 that will become the Si ion implantation layer 6 by vapor phase chemical deposition technology (CVD technology) or the like.
A G (phosphorus/silicon oxide glass) coating 7 is formed. Si, N instead of this PEG.

Alternatively, AltO3 (aluminum oxide) may be precipitated. (Fig. 2) (3) By performing wet etching with a hydrogen fluoride-based etchant or dry etching using a heptafluoride-based gas on the coating 7 using a photoresist mask,
A groove (vertical and horizontal groove) 9 as shown in FIG. 6 is made. In this case, the substrate surface is not etched and the grooves are provided on the scrub line, that is, in the substrate dividing area. (Figure 3) (4) Annealing is performed by heating the substrate 1 at 500°C to 1,000°C for about 20 minutes with the groove 9 covered with the film to diffuse the ion-implanted Si. Then, an n-type active layer 2 of a predetermined depth and an n+ diffusion layer 3 for osmic contact of source/drain electrodes are formed on the main surface of the substrate.

(Fig. 4) (5) Next, remove the coating such as the above PSG and create a new KCV.
A surface protection insulating film made of D = PSG or CvD-8iO1 is provided, the contact portion is opened using photoresist technology, and then source-drain electrodes 4 are formed using a "lift-off" method using a photoresist mask. A GaAs FET is completed by forming a gate electrode 5 made of Schottky metal such as Al in the gate portion.

(FIG. 5) Although the case where the film on the scrub line is removed has been described above, the present invention is not limited thereto.

That is, the above-mentioned film only needs to be present on the element formation region.

〔Effect of the invention〕

According to the present invention described in the embodiments above, the following effects can be obtained.

By providing a film such as KPSG on one principal surface of the GaAs substrate and making a groove in this film, and performing activation annealing on the GaAs substrate covered with this film, it is possible to eliminate the problems that would occur during annealing if the groove was not made. Thermal strain due to the difference in thermal expansion coefficient between the substrate and the coating can be prevented. That is, thermal stress is absorbed by the grooves and no thermal strain occurs. This prevents carriers from being trapped in the strained layer in the substrate (and improves the active yield of the Si ion implanted layer).

The above describes the case where the film on the scrub line is removed.

[Application field]

The present invention is also effective when applied to annealing of ion-implanted layers of compound semiconductors including GaAsFETs and GaAs ICs.

In addition to the above, the present invention can also be applied to compound semiconductor optical devices.

[Brief explanation of drawings]

1 to 5 show an embodiment of the present invention.
FIG. 3 is a partial step cross-sectional view in the manufacturing process of 3 semiconductors. FIG. 6 is a plan view of the quefer in the process shown in FIG. 4. FIG. 7 is a sectional view showing an example of a GaAs MESFET. FIG. 8 is a sectional view showing a mode of annealing a GaAs substrate. 1... GaAs substrate, 2... n-type active layer, 3...
n-type diffusion layer, 4... source/drain electrode, 5...
- Gate electrode, 6... Ion implantation impurity, 7... Film, 8... Insulating film, 9... Scribe groove. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6rIA Figure 7 Figure 8?

Claims (1)

[Claims] 1. A step of selectively forming an impurity ion implantation layer in an element formation region on one main surface of a wafer-shaped compound semiconductor substrate, and preventing the impurities from escaping onto the main surface. A method for manufacturing a compound semiconductor device, comprising the steps of forming a film of a substance, selectively removing at least a portion of the film other than a portion covering an element formation region, and performing heat treatment. 2. The compound semiconductor device according to claim 1, wherein the portions from which the film is selectively removed are divided regions of the compound semiconductor substrate, and the film is removed in a grid pattern. . 3. The method of manufacturing a compound semiconductor device according to claim 1, wherein the compound semiconductor is GaAs, and the coating for preventing impurity dissipation is a phosphorus-silicon oxide glass.