JPS60242717A - Fir-type digital filter - Google Patents

Abstract

PURPOSE:To obtain reproduced sound of plural channels where the phase is arranged completely even when a single D/A converter is used by setting individually a coefficient different from a prescribed amount depending on plural channels and using the coefficient switchingly corresponding to each channel. CONSTITUTION:When D/A conversion is required for an L channel, a switch circuit 16 is thrown to the position of a contact (a), a digital signal fed from an input terminal 10 is delayed sequentially by a prescribed amount at a shift register 11 and a RAM12 and fed to a multiplier 13 as a data. The data is multiplied sequentially at the multiplier 13 with a multiplication coefficient corresponding from a ROM14. Then the multiplied output of the multiplier 13 is fed sequentially to an adder 17, added with a feedback input from an accumulator 18, and when the addition is executed repetitively, an output of the accumulator 18 is fed to a shift register 19, the content of the shift register 19 is extracted at an output terminal 20 as a desired L channel digital signal and fed to a D/A converter.

Description

[Detailed Description of the Invention] Industrial Application Field This invention is used for digital-to-analog conversion (hereinafter referred to as D/A conversion) using stereo time division processing of data sampled simultaneously from multiple channels. The present invention relates to a preferred F I RJ digital filter.

BACKGROUND TECHNOLOGY AND PROBLEMS L channel and R channel (data of multiple channels are sampled alternately with a predetermined phase difference)
ζ In the case of recording, there is no problem in using a single D/A converter for time-division processing during playback, but for example, as with data recorded on a compact disc player disc,
In cases where L channel and R channel data are sampled and recorded at the same time, if a single D/A converter is used for time division processing during playback, the 1/2 fs (fs is the sampling frequency after oversampling, usually 44.1k)
This causes the inconvenience that the phase is shifted by Iz x 2) x 1/2 (seconds).

Therefore, conventionally, for applications where it would be a problem to cause a phase difference between the L channel and the R channel, time-division processing was stopped and a dedicated D/A converter was used for each channel to perform simultaneous D/A conversion. A conversion processing was performed. Therefore, there are disadvantages in that the structure becomes complicated and the cost becomes high on the market.

It is also conceivable to provide an analog delay circuit (temple hold circuit) after the D/A converter to eliminate the phase difference between the L channel and R channel after D/A conversion.
It is impractical and is not used in practice.

Purpose of the Invention In view of the above, the present invention proposes an FIR type digital filter that can obtain reproduced sound of multiple channels with completely aligned phases even when using a single D/A converter. It is.

Summary of the Invention In the present invention, in an FIR type digital filter that performs data interpolation by time-division processing of multiple channels, coefficients are set for each of the multiple channels individually and each other by a predetermined amount, and these coefficients are It is designed to be used by switching according to each channel. As a result, according to the present invention, even with stereo time-division processing using a single D/A conversion, it is possible to reproduce a plurality of channels with completely aligned phases.

EXAMPLE Hereinafter, an example of the present invention will be described in detail based on FIGS. 1 to 4.

FIG. 1 shows a conventional FIR type digital filter,
Delay devices (11), (12)... (IN) having a delay amount equal to the sampling period of input data, and coefficients KO, 1...KN-1 for each delay output. Multiplier (2t), (22)...(2N
) and an adder (3) that adds the outputs of each multiplication. Delay device (11), (12)...
- (IM) usually consists of a shift register, RAM, etc., and its operating clock is an integral multiple of the basic sampling frequency fs.

Now, the unit sample response of this digital filter is h
(n), the system function (transfer function) H(Zl
is expressed by the following formula.

Moreover, the coefficient K n (n-0 to N-1) is Kn・=
h(nl...(2)).

The frequency response of a filter having such a system function is expressed by Z=e''.

From the above equation (2), the coefficient K of the FIR type digital filter is
It can be seen that n is the unit sample response h (n) itself.

Next, we will discuss how to calculate the unit sample response h(n).

There are methods for calculating this unit sample response, such as Chebyshev approximation and equiripple approximation, but here we will explain a method using ideal low-pass inverse Fourier transform, that is, a method for calculating from the impulse response of an analog filter.

First, let F be the frequency characteristic, then its time function f
Ttl is obtained by inverse Fourier transform.

Here, the frequency characteristic F(ω) is an ideal low-pass as shown in FIG. So, the time function r (
t) is expressed by the following formula.

π t When this equation (5) is modified as a function of discrete time, it becomes. However, in the above equation (6), t=nT (T= 1
/fs, n is an integer), (IIC=2πfc (fc is the cutoff frequency). Note that fs is the oversampling frequency of the filter.

Here, the impulse response of the analog filter is ha(t
l, and the unit sample response of the corresponding digital filter is hd(nl (n = 0 to N-1), then
To approximate the characteristics of an analog filter including its gain, the unit sample response of a digital filter is expressed as hd(nl = T ha (n T )...
It may be set to 71. Note that ha is multiplied by 1 for normalization in order to compare the unit areas of both functions.

Therefore, from equations (6) and (7) above, the unit sample response of the digital filter can be determined.

Next, in order to apply this to the circuit configuration shown in Figure 1, the above (
The unit sample response h tn> used in equation 2) is expressed as ha(
n). To do so, the following must be satisfied in order to form a linear phase FIR type digital filter: h(n) = h (N-1-n) = = f91. Then, n in the above equation (8) should be shifted so that -1 hd(01= h (-) ...α0. In other words, h (nl-K n ). In other words, this ( Equation 11) means that there is a direction in which the unit sample response hd(nl) of the dicicle filter is substantially positive.

Now, considering the group delay characteristic of this filter, this group delay characteristic substantially depends on the number of stages (number of taps) N of the filter and the number of oversampling subwaves fs, and is determined by the following equation.

-1 In other words, it is the shift amount - shown by the above aφ formula multiplied by 1/fs, which is constant.

Therefore, N in equation (12) above does not represent an arbitrary number of stages! By substituting and l+1, which is one step different from this, and taking the difference between the two, the following equation is obtained.

This is the amount of delay that must be corrected when time-divisionally performing D/A conversion between multiple channels, for example, the L channel and the R channel.

Data sampled simultaneously during normal recording is
In the case of channel and R channel, D/A conversion is performed in the order of L channel and R channel during playback, so ■
, the R channel is larger than the R channel, and in order to compensate for this, it is sufficient to set N for the L channel to be 1 larger than for the R channel.'' (13)
It can be understood from the formula.

Therefore, with such a setting, the delay amount is greater than that of the digital filter channel, and as a result, L channel and R channel signals having completely aligned phases can be obtained after D/A conversion.

Figure 3 is a neo version of one embodiment of this invention.
This is a case where the present invention is applied to a type of digital filter that performs multi-channel switching by D/A conversion.

In the same figure, aω is an input terminal to which a digital signal is supplied, (11) is a shift register that sequentially takes in digital signals from the input terminal (+01), and (12) is used to write and read the contents of the shift register (11). RAM
So, this RAM (12) is, for example, 16X 27
(16X'14 (Lch) '+16X 13
(Rch) ) bit capacity.

(13) is a multiplier in which the output of RAM (12) is treated as data and is supplied to one of its input sides. For example, in this case, when considering both channels, 16 [bits] x 16 ( bit) x 53 (27+26)
Assume that there is a multiplication ability of [times]. (1,4).

(15) is an RO in which multiplication coefficients used in D/A conversion of the upper channel and R channel are stored in advance, respectively.
In this case, for example, the ROM (14) is 16X
The capacity of the ROM (15) is 27 bits, and the capacity of the ROM (15) is 16×26 bits. (16) is ROM (14) (15)
This is a switch circuit that switches the output of the ROM (14
) and the multiplication coefficient from the ROM (15) which is switched to the contact side during D/A conversion of the R channel, respectively, are supplied to the other input side of the multiplier (13).

(17) is an adder that adds the multiplication output of the multiplier (13), and (18) is an accumulator that launches the result of the adder (17), and a part of the output of this accumulator (18) is sent to the adder. (17) and is fed back to the successive multiplier (13
), for example, T=2 in this\
During /fs, addition is performed 25 times during D/A conversion of the L channel and 24 times during D/A conversion of the R channel.

(19) is the shift 1/sister to which the output of the accumulator (18) is supplied, (20) is the shift register (19)
This is the output terminal taken out from the

Next, the operation of this circuit will be explained. L channel D/A
At the time of conversion, the switch circuit (16) is connected to the contact a side, and the digital signal supplied from the input terminal 00) is sequentially delayed by a predetermined amount in the shift register (Jl) and RAM (12), and is sent as data to the multiplier (13). ) and are sequentially multiplied by the corresponding multiplication coefficients from the ROM (14). Then, the multiplication output of the multiplier (13) is sequentially supplied to the adder (17) and added to the previous multiplication output, that is, the feedback input from the accumulator (18), and the repetition of this addition operation is 25 in this case. Once the output of the accumulator (18) is supplied to the shift register (19), the contents of this shift register (19) are changed to the desired one.
Output terminal (20) as a 2-channel digital signal
The signal is taken out and supplied to a D/A converter (not shown).

Also, during D/A conversion of the R channel, the switch circuit (16) is switched to the contact side, and the input terminal (
The digital signal from 101 is sent to the shift register (11)
The signals are sequentially delayed by a predetermined amount in the RAM (12) and supplied as data to the multiplier (13), where they are sequentially multiplied by the corresponding multiplication coefficients from the ROM (15). Then, the multiplication output of the multiplier (13) is sequentially supplied to the adder (17) and added to the feedback power from the accumulator (18), and when this addition operation is repeated 24 times in this case,
The output of the accumulator (18) is the shift register (19).
), its contents are taken out as a desired R-channel digital signal at an output terminal (20), and supplied to a D/A converter (not shown).

Figure 4 shows the group delay amount in each channel when the size of N is shifted by 1, such as N-27 for the L channel and N-26 for the R channel, as described above. It can be seen that the group delay amount of the unseen channel is 13T, and as shown in FIG. 4B, there is a difference in the amount of group delay of the R channel.

■ Therefore, by supplying such R channel and - signals to the D/A converter and time-sharing processing, the D/A converter normally processes the L channels. So,
As a result, an in-phase L channel signal and an L channel signal with the phase difference between the L channel and R channel corrected are obtained on the output side of the D/A converter.

In this way, °ζ is the L channel in this embodiment.

Coefficients are allocated independently for the R channel, the number of these two types (number of stages) differs by l between the L channel and the R channel, and these coefficients are switched and used depending on the L channel and the R channel. Therefore, it is possible to realize an oversampling filter that can also correct the phase difference between the L channel and the R channel.

Effects of the Invention As described above, according to the present invention, in an FIR type digital filter that performs data interpolation by time-division processing of multiple channels, that is, performs oversampling to shift the sampling rate, the multiple channels are individually and mutually processed. By setting coefficients that differ by a predetermined amount and switching between these coefficients in accordance with each channel, even with stereo time-sharing processing using a single D/A conversion, it is possible to reproduce completely phase-aligned multiple channels. This makes it possible to simplify the circuit configuration and reduce costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional FIR type digital filter, FIG. 2 is a diagram showing ideal low-pass frequency characteristics, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. This figure is a diagram for explaining the operation of FIG. 3. (11) and (19) are shift registers, (12) is R
AM, (13) is a multiplier, (14) and (15) are RO
M, (17) is an adder, and (18) is an accumulator. Figure 1 Figure 3

Claims (1)

[Claims] F that performs data interpolation by time-sharing processing of multiple channels
An FIR type digital filter characterized in that coefficients are individually set for the plurality of channels and different from each other by a predetermined amount, and the coefficients are switched and used in accordance with each channel.