JP3513508B2 - Recording / playback device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal synthesizing method for synthesizing a plurality of signals by a simple process.

[0002]

2. Description of the Related Art Conventionally, in order to synthesize a plurality of signals such as a stereo audio signal to obtain a synthesized signal, the following processing has been performed on an analog signal and a digital signal.

In the case of an analog signal, generally, an analog arithmetic circuit as shown in FIG. 6 or 7 is used to perform signal synthesis. In the adding circuit shown in FIG. 6, resistors R ₁₁ and R ₁₂ provided in parallel are connected to the inverting input terminal of the operational amplifier 11, and the resistor R ₁₃ is provided between the inverting input terminal and the output terminal of the operational amplifier 11. Are connected and configured as an inverting amplifier circuit. In this adder circuit, the resistors R _{11 to} R _{13 are}
When the resistance values of all are set equal, the input signal V
_{When 1} · V ₂ is input to the resistors R ₁₁ and R ₁₂ , respectively,
A combined signal V _{01 of} V ₀₁ = − (V ₁ + V ₂ ) is obtained.

In the subtractor circuit shown in FIG. 7, resistors R ₂₁ and R ₂₂ are connected to the inverting input terminal and the non-inverting input terminal of the operational amplifier 21, respectively, and the inverting input terminal and the output terminal of the operational amplifier 21 are connected. A resistor R ₂₃ is connected in between, and the above-mentioned non-inverting input terminal is grounded via a resistor R _24, which constitutes a differential amplifier circuit. In this subtraction circuit, when the resistance values of the resistors R _{21 to} R ₂₄ are all set to be equal, the input signals V ₁ and V ₂ are respectively input to the resistor R _21.
When input to the R ₂₂ side, a composite signal V _{02 of} V ₀₂ = V ₂ −V ₁ is obtained.

On the other hand, in the case of a digital signal digitized with a plurality of bits (for example, 16 bits), FIG.
Signal synthesis is performed using a digital signal processing circuit (DSP) 31 as shown in FIG. This digital signal processing circuit 3
1 is an arithmetic processing unit 3 that performs arithmetic processing by software.
Have two. For example, in the arithmetic processing unit 32,
Since it has a function of executing arithmetic processing by software, it apparently adds multipliers 33 and 34 for multiplying the input signals S ₁ (I) and S ₂ (I) by a predetermined coefficient, and these arithmetic results. And an adder 35.

In the digital signal processing circuit 31 as described above, the addition, subtraction, multiplication and division of the input signals S ₁ (I) and S ₂ (I) is performed by a combination of the operations of the multipliers 33 and 34 and the adder 35. It is possible to carry out, and the combined signal S ₀ (I) is obtained by the arithmetic processing.

[0007]

However, the above-mentioned circuit for synthesizing analog signals and the circuit for synthesizing digital signals have the following problems, respectively. (1) In case of analog signal a) Since it is formed by an analog circuit, the circuit configuration becomes complicated.

B) Since an analog circuit is used, sufficient accuracy of signal synthesis cannot be obtained due to variations in characteristics of circuit elements. Since the characteristics of the circuit element also vary depending on the surrounding environmental conditions such as temperature and humidity, it is necessary to consider this point as well in order to obtain sufficient signal synthesis accuracy. In order to obtain sufficient accuracy, it is necessary to use expensive circuit elements with stable characteristics.

C) The original signal cannot be restored from the signal once synthesized. (2) In the case of digital signal a) The digital signal processing circuit 31 is very expensive,
This leads to an increase in the price of a device incorporating the digital signal processing circuit 31.

B) It is not possible to restore the original signal from the signal once synthesized.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to perform signal combining with a simple configuration and restore the original signal from the combined signal.

[0012]

The present invention is characterized in that a plurality of 1-bit digital signals are combined in a time division manner so that they can be handled as a single signal and can be restored to the original signal.

Further, the present invention is characterized in that a stereo audio signal is used as the plurality of 1-bit digital signals, while the time-combined signal is treated as a monaural signal.

The above-mentioned 1-bit digital signal refers to a 1-bit digital signal obtained by high-speed sampling ΔΣ modulation or the like, and is completely different from the PCM signal used in general digital signal processing. It is different.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] The following will describe one embodiment of the present invention with reference to FIGS.

As shown in FIG. 1, the signal synthesizing apparatus according to the present embodiment includes signal sources 1 and 2, a time division signal synthesizing circuit 3, and
And a gate timing control circuit 4.

The signal sources 1 and 2 are 1-bit digital signals S corresponding to a left channel (Lch) signal and a right channel (Rch) signal of a stereo audio signal, respectively.
_This is a circuit that generates ₁ (I) · S ₂ (I). Signal source 1.2
Operates at the timing of the clock CLK, and the 1-bit digital signal S ₁ (I)
It is designed to output S ₂ (I). Also, the signal source 1
2 may be a signal for generating a 1-bit digital signal by performing processing such as high-speed sampling ΔΣ modulation on an analog signal or a digital signal of a plurality of bits (for example, 16 bits).

The time-division signal synthesizing circuit 3 as the first synthesizing means has the above-mentioned 1-bit digital signals S ₁ (I) and S ₂ (I).
Is a circuit for alternately rearranging and synthesizing on the time axis at an interval of ΔT / 2 determined by the timing signal generated by the gate timing control circuit 4. The time-division signal synthesizing circuit 3 also operates at the timing of the clock CLK.

The time-division signal synthesizing circuit 3 is composed of, for example, a so-called logic circuit as shown in FIG. In this circuit, the AND circuit 3a receives the 1-bit digital signal S ₁ (I) and the timing signal from the gate timing control circuit 4, and the AND circuit 3b receives the 1-bit digital signal S ₂ (I) and the timing signal. Signal is N
The signal inverted by the OT circuit 3c is input.
The output signals of the AND circuits 3a and 3b are both input to the OR circuit 3d, and the combined signal S is output from the OR circuit 3d.
₀ (I) is output.

The gate timing control circuit 4 as the first time ratio setting means divides the clock CLK to obtain a pulse having a period of ΔT, and further sets the duty of the pulse to 50% to obtain ΔT / 2. It is a circuit for generating timing signals at intervals of, and is adapted to set the time ratio of the time division in the time division signal synthesizing circuit 3.

In the above configuration, the 1-bit digital signal S ₁ (I) output from the signal source 1 is "0" or "1" at every sampling period ΔT as shown in FIG.
Signals _{L 1 · L 2 · L 3} ... are Lch signal formed continuously. The 1-bit digital signal S ₂ (I) output from the signal source 2 is "0" at every sampling period ΔT.
Alternatively, "1" signals R ₁ , R ₂ , R _3, ... Are Rch signals that are continuously formed. On the other hand, the gate timing control circuit 4 generates a timing signal at intervals of ΔT / 2, and this timing signal is output to the time division signal synthesis circuit 3.

The above 1-bit digital signal S ₁ (I)
S ₂ (I) is latched at intervals of the sampling period ΔT in the time division signal synthesizing circuit 3 and is rearranged alternately on the time axis according to the above timing signal. As a result,
As shown in FIG. 3, the 1-bit digital signal S ₁ (I)
A combined signal S _{0 obtained} by combining S ₂ (I) in the same cycle ΔT / 2
(I) is obtained. This combined signal S ₀ (I) becomes a monaural signal [(L + R) / 2 signal] in which the Lch signal and the Rch signal are added and combined at an equal ratio.

As described above, in the signal synthesizing device of this embodiment, the 1-bit digital signal is time-divisionally synthesized, so that the signal synthesizing process can be easily performed. Further, by combining the signals in a time division manner, the signal information before the combining is saved, and the original signal can be restored.

[Second Embodiment] The following will describe another embodiment of the present invention with reference to FIGS. 4 and 5. In the present embodiment, constituent elements having the same functions as those of the circuits and the like described in the first embodiment will be designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 4, the signal synthesizing apparatus according to the present embodiment includes signal sources 1 and 2, an inverting circuit 5, a time division signal synthesizing circuit 6, and a gate timing control circuit 7. .

The inverting circuit 5 is provided between the signal source 2 and the time division signal synthesizing circuit 6 and is a circuit for inverting the state of the 1-bit digital signal from the signal source 2.

The time-division signal synthesizing circuit 6 as the second synthesizing means has the 1-bit digital signal S ₁ (I) and the 1-bit digital signal S ₂ (I) inverted by the inverting circuit 5 in the 1-bit state. It is a circuit for arranging the digital signal S ₂ '(I) and arranging them alternately on the time axis at intervals determined by the timing signal generated by the gate timing control circuit 7 and synthesizing them. The time-division signal synthesis circuit 6 operates at the timing of the clock CLK.

The gate timing control circuit 7 as the second time ratio setting means controls the duty of the pulse of the period ΔT obtained by dividing the clock CLK, thereby performing the time division in the time division signal synthesizing circuit 6. It is a circuit that generates a timing signal that determines the time ratio, and is adapted to variably set the time ratio of the timing signal.

In the above configuration, the 1-bit digital signal S ₁ (I) output from the signal source 1 is "0" or "1" at every sampling period ΔT as shown in FIG.
Signals _{L 1 · L 2 · L 3} ... are Lch signal formed continuously. The 1-bit digital signal S ₂ (I) output from the signal source 2 is "0" at every sampling period ΔT.
Alternatively, a signal R ₁ ′ · R ₂ ′ · R, which is in one of the states “1”, but whose state is inverted from the original signal by the inverting circuit 5.
_It becomes a 1-bit digital signal S ₂ '(I) composed of ₃ ' ... (R'ch signal).

On the other hand, in the gate timing control circuit 7,
For example, a timing signal having a time ratio that divides the sampling period ΔT into 3: 1 is generated. This timing signal is output to the time division signal synthesis circuit 6.

The above-mentioned 1-bit digital signal S ₁ (I)
S ₂ ′ (I) is latched by the time division signal synthesizing circuit 3 at intervals of the sampling period ΔT and is rearranged alternately on the time axis according to the timing signal. As a result, as shown in FIG. 4, the 1-bit digital signal S
A combined signal S ₀ (I) obtained by combining ₁ (I) · S ₂ ′ (I) at a time ratio of 3ΔT / 4: ΔT / 4 is obtained. The synthesized signal S ₀ (I) is a signal obtained by subtracting the R'ch signal at a time interval of 1/3 of the Lch signal from the Lch signal and synthesized [[3
LR ′) / 4 signal].

As described above, in the signal synthesizing apparatus of this embodiment, the 1-bit digital signal is time-divisionally synthesized as in the case of the first embodiment. Therefore, the signal synthesizing process can be performed easily. It becomes possible to restore the original signal.

Further, in the present signal synthesizing apparatus, the gate timing control circuit 7 can change the time ratio of the time division in the time division signal synthesizing circuit 6, so that the signal synthesizing can be performed at an arbitrary ratio. it can.

[0034]

As described above, according to the present invention, by combining a plurality of 1-bit digital signals in a time division manner, they can be handled as a single signal and can be restored to the original signal. For example, by using a stereo audio signal as the plurality of 1-bit digital signals, it is possible to handle a signal that has been time-divisionally combined as a monaural signal and to easily restore the stereo signal. Play.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a signal synthesizing apparatus according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a time division signal combining circuit in the signal combining device of FIG.

FIG. 3 is an explanatory diagram showing two 1-bit digital signals and a signal synthesized by the signal synthesizer of FIG.

FIG. 4 is a block diagram showing a schematic configuration of a signal synthesizing apparatus according to another embodiment of the present invention.

5 is an explanatory diagram showing two 1-bit digital signals and a signal synthesized by the signal synthesizer of FIG. 4. FIG.

FIG. 6 is a circuit diagram showing a conventional analog signal synthesizer.

FIG. 7 is a circuit diagram showing another conventional analog signal synthesizer.

FIG. 8 is a circuit diagram showing a conventional digital signal synthesizer.

[Explanation of symbols]

1 Signal source (Lch) 2 Signal source (Rch) 3 time division signal synthesis circuit 4 Gate timing control circuit

Claims (2)

(57) [Claims] 1. A single signal can be handled by combining a plurality of 1-bit digital signals in a time division manner,
And a signal processing method characterized by being able to restore the original signal. 2. The signal processing method according to claim 1, wherein a stereo audio signal is used as the plurality of 1-bit digital signals, and the signals time-divisionally combined are treated as a monaural signal.