JPS60242380A - Facilitating circuit for fault diagnosis of integrated circuit - Google Patents

Abstract

PURPOSE:To constitute the diagnosis facilitating circuit with the smallest number of diagnostic pins by dividing the integrated circuit into several diagnostic blocks under mode control through a selector, using input and output pins of the circuit in common on time-division basis, and taking a time-division diagnosis. CONSTITUTION:The circuit to be diagnosed is divided into blocks 1-3 and a diagnosing circuit consists of diagnostic block division selectors 5 and 6, diagnostic mode changeover selectors 4 and 7 for input and output signal pins A and B, a selector mode changeover pin C, a shift register 8, flip-flops 9-11, a shift register 12, and driving clock pins D and E. Then, serial data are inputted from the input signal pin A in diagnostic mode and converted by the shift register 8 into parallel data, which are supplied to latches 9-11 to obtain diagnostic data classified by the blocks. Then, parallel data on the diagnostic result on each block are converted by the shift register 12 into serial data, which is outputted.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to fault diagnosis of integrated circuits, and is particularly a fault diagnosis facilitation circuit suitable for fault diagnosis of high-density packaging integrated circuits. .

[Background of the invention]

In conventional integrated circuit diagnosis, as shown in Figure 1, some of the multiple external terminals are assigned to diagnostic terminals, and internal wiring is connected directly from the internal part that is not being observed to the diagnostic terminals. This method uses a method of extracting internal signals using
As shown in FIG. 2, the internal signal is once output to an external terminal for diagnosis, and then the device is strapped for use during actual use, thereby making diagnosis easier. but,
If these methods are used, the number of bins required for diagnosis will increase as the integrated circuit becomes highly packaged and large-scale, but diagnosis becomes difficult due to the limited number of terminals possessed by the integrated circuit itself. There were a few shortcomings.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a diagnosis facilitation circuit which solves the conventional problems and facilitates the diagnosis of internal logic gates with a minimum number of diagnostic bins even in a highly densely packaged integrated circuit.

[Summary of the invention]

In order to achieve the above object, the present invention divides a high-density packaging integrated circuit into several diagnostic blocks, provides a selector between these diagnostic blocks, and performs mode control using a control circuit to divide the circuit into each diagnostic block. Then, the integrated circuit input bins and output bins are shared in a time-sharing manner,
Diagnosis is performed by inputting and outputting the diagnostic information of each professional by multiplexing it in the form of serial data.

[Embodiments of the invention]

An embodiment of the present invention will be explained below with reference to FIG. In this embodiment, the circuits to be diagnosed (blocks 1 to 5), their input/output signal bins (A and B), and a selector 5 for grouping the circuits into blocks to facilitate diagnosis.
~6. Selectors 4 and 7 for switching input/output signal bins A and B to diagnostic mode. Selector mode switching bin C9 Shift register 8 and F9 for setting diagnostic data from the selector to each block in the diagnostic mode. Pflop 9-11. Shift register 12 for reading diagnostic data. This is an integrated circuit composed of driving clock input bins D and E. Selector control pin C during diagnosis
Then, the selectors 4 to 7 are switched to the b, d, f, and h sides, respectively.

How to set diagnostic data to each block 1 to 3 will be explained with reference to a timing chart in FIG. now,
The diagnostic data of block 1 is bl, b2. b3. b4.
b5, dl that of block 2, d2. d3, d4.
, dhepro, that of ri6, fl, f2. f3. f4. f
5 (b1~b5.d1~d5.f1~f5 are each 11"
or 10''), input signal bin A
From' fl, dl, bl, f2. d2. b2. , f3
．． d3. b3. f4. d4. b4°f5. d5. b5″
I will input the Syrian ν data. Convert it to parallel data by shift register 8, and
9 to 11 are used as diagnostic data for each block.

Next, how to read the diagnostic data of each block will be explained with reference to the timing chart of FIG. Now, the output C of Pro, Ri1 is cl.

c2. c3. c4. c5 pro, ri2 output e is el, e
2. e5゜e4. e5, the output g of block 3 is gl,
g2. g5. g4. g5 (C1-C5, 01-859g
1 to g5 are each 1 or 10''), the shift register 12 transfers the above parallel data to serial data 1cl, ei, gl, c2.e.
2. g2. c5. e3. g5. c4. e4. g4. c5
．． It is possible to convert it into the form e5°g5, read it out, and observe it.

In this way, by dividing several programs using selectors and using real signal input and output bins and register groups to time-divisionally set and read diagnostic data, it is possible to divide the real signal input and output bins. can be used as a diagnostic input/output bin.

According to this embodiment, a selector, an input/output register group, a selector control bin, and a register drive clock.

By using more input bins, it is possible to diagnose internal logic gates with a minimum number of diagnostic bins.

〔Effect of the invention〕

According to the diagnostic facilitation circuit of the present invention, by using a selector, its control input bin, a group of input/output registers for interconverting serial data and a parallel gate, and a clock input bin for driving the selector and its control input bin, The diagnostic bin has the effect of making it possible to diagnose failures of internal logic gates in horizontal circuits.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are circuit diagrams of a conventional diagnosis facilitation circuit;
3 to 5 each show an embodiment of the present invention, and FIG. 3 is a circuit diagram of a diagnosis facilitation circuit, and FIGS.
The figure shows a timing chart for setting and reading the input/output data. 1 to 3...Diagnostic blocks 1 to 3.4 to 7...Mode switching selectors 4 to 7.8...Input data, serial-parallel conversion register group, 9 to 11...Diagnostic data Setting use, TE, 12...Diagnostic output data, register group for parallel to serial conversion. Representative Patent Attorney Akio Takashi Figure 1 Figure 2 Diagnosis and Cutting Pins

Claims (1)

[Claims] When diagnosing the failure of an integrated circuit, multiple selectors, their control circuits, and control input terminals are provided to divide the circuit to be diagnosed into several parts, as well as their control circuits and control input terminals. A plurality of registers for supplying data, a plurality of registers for reading diagnostic data from the circuit under diagnosis, and a diagnostic clock input terminal for supplying clock signals for driving the above registers are provided, and each divided diagnostic section is equipped with On the other hand, an integrated circuit is characterized in that failure diagnosis of internal logic gates can be easily performed within the range of a certain number of input/output terminals by setting diagnostic data from the actual signal terminals in a time-sharing manner. Fault diagnosis facilitation circuit.