JPS6314445A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS6314445A
JPS6314445A JP61158254A JP15825486A JPS6314445A JP S6314445 A JPS6314445 A JP S6314445A JP 61158254 A JP61158254 A JP 61158254A JP 15825486 A JP15825486 A JP 15825486A JP S6314445 A JPS6314445 A JP S6314445A
Authority
JP
Japan
Prior art keywords
circuit
parallel
serial
test
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61158254A
Other languages
Japanese (ja)
Inventor
Jun Ito
潤 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61158254A priority Critical patent/JPS6314445A/en
Publication of JPS6314445A publication Critical patent/JPS6314445A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the number of applicable terminal members for testing inside an integrated circuit by a method wherein a parallel/serial conversion circuit and a serial/parallel conversion circuit are inserted into an input output or both of them of a tested circuit. CONSTITUTION:A serial parallel conversion circuit 5 or a circuit outputting test signal through a parallel/serial conversion circuit 6 is contained in an input part of test signal inside an integrated circuit 1 to perform the functional test of specific part 3 inside the integrated circuit 1. For example, control signal is inputted from a control signal input terminal 13 to switch off a test signal input and output terminal 17, a test result output and input terminal 18 and a selector 4 for turning off the tested circuit 3 from an inner circuit 2 as well as for inputting the test signal from the test signal input and output terminal 17 to the parallel through the serial/parallel conversion circuit 5. Finally, a result signal outputted to the parallel is converted into serial by the parallel/ serial conversion circuit 6 to be outputted from the test result output and input terminal 18.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路に関し、特に、集積回路内部の特定部
分の機能試験機構並びに試験回路の構成に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit, and more particularly to a functional test mechanism for a specific portion inside an integrated circuit and a configuration of the test circuit.

〔従来の技術〕[Conventional technology]

従来、この種の集積回路では、第3図に示す様な集積回
路1の内部回路2゛の被試験回路3のみの機能試験を実
施するためには、第2因に示す様に入力専用端子11、
出力専用端子10を双方向端子とした上で、制御信号入
力端子13を1本以上設置し、かつ被試験回路2の入力
部並びに出力部にセレクタ4を設置する構成となってい
た。このとき、制御信号入力端子13から制御信号を入
力することKより双方向端子の入出力方向を制御するこ
とKより入力端子化した双方向端子15並びに1出力端
子化した双方向端子16を実現し、同時にセレクタ4を
切り替えることにより被試験回路3を内部回路2から切
り放した上で、試験信号を15より入力し、被試験回路
3の機能試験を実   ゛施し、その結果を16より外
部に取り出す様な回路動作となっていた。
Conventionally, in this type of integrated circuit, in order to perform a functional test of only the circuit under test 3 of the internal circuit 2 of the integrated circuit 1 as shown in FIG. 11,
The configuration is such that the output-only terminal 10 is a bidirectional terminal, one or more control signal input terminals 13 are installed, and the selector 4 is installed at the input section and output section of the circuit under test 2. At this time, inputting a control signal from the control signal input terminal 13, controlling the input/output direction of the bidirectional terminal from K, and realizing a bidirectional terminal 15 which is an input terminal and a bidirectional terminal 16 which is a single output terminal. At the same time, the circuit under test 3 is disconnected from the internal circuit 2 by switching the selector 4, the test signal is input from 15, a functional test is performed on the circuit under test 3, and the results are transmitted externally from 16. The circuit operated as if it were being taken out.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の集積回路では、入力専用又は出力専用と
なっている端子を双方向端子とする事によシ試験信号の
入力および被試験回路からの信号の出力を行なう構成と
なっているため、使用するパッケージにより集積回路内
部の被試験回路を試験するために必要々端子数に対して
使用可能な端子数が不足する場合があるという欠点があ
りた。
The above-mentioned conventional integrated circuit is configured to input test signals and output signals from the circuit under test by converting input-only or output-only terminals into bidirectional terminals. Depending on the package used, there is a drawback that the number of usable terminals may be insufficient compared to the number of terminals required to test the circuit under test inside the integrated circuit.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の集積回路は集積回路内部の試験用にパラレル・
シリアル変換回路、又はシリアル・パラレル変換回路、
又は、その双方を有している。
The integrated circuit of the present invention can be used in parallel for internal testing of the integrated circuit.
Serial conversion circuit or serial-parallel conversion circuit,
Or have both.

〔実施例〕〔Example〕

次に本発明について1図面を参照して説明する。 Next, the present invention will be explained with reference to one drawing.

第1図は、本発明の一実施例の構成図である。FIG. 1 is a block diagram of an embodiment of the present invention.

1は集積回路全体、2は内部回路、3は被試験回路、4
はセレクタ、5はシリアル・パラレル変換回路、6はパ
ラレル・シリアル変換回路、10は出力専用端子、11
は入力専用端子、13は制御信号入力端子、17は試験
信号入力兼出力端子、18は試験結果出力兼入力端子で
、制御信号入力端子13より制御信号を入力することに
より、試験信号入力兼出力端子17、試験結果出力兼入
力端子18、セレクタ4を切り替えることにより被試験
回路3を内部回路2より切り放して、被試験回路3を外
部と直結した上で試験信号入力兼出力端子17より、試
験信号をセレクタ4を通じてシリアル・パラレル変換回
路5に入力し、試験信号を被試験回路3にパラレルに入
力する。ここで、被試験回路3よりパラレルに出力され
た結果信号は、セレクタ4を通じてパラレル・シリアル
変換回路により、シリアルに変換され、試験結果出力兼
入力端子18より出力される。
1 is the entire integrated circuit, 2 is the internal circuit, 3 is the circuit under test, 4
is a selector, 5 is a serial/parallel conversion circuit, 6 is a parallel/serial conversion circuit, 10 is an output-only terminal, 11
is an input-only terminal, 13 is a control signal input terminal, 17 is a test signal input/output terminal, 18 is a test result output/input terminal, and by inputting a control signal from the control signal input terminal 13, the test signal can be input/output. By switching the terminal 17, the test result output/input terminal 18, and the selector 4, the circuit under test 3 is disconnected from the internal circuit 2, the circuit under test 3 is directly connected to the outside, and then the test signal input/output terminal 17 is connected to the test signal input/output terminal 17. The signal is inputted to the serial/parallel conversion circuit 5 through the selector 4, and the test signal is inputted to the circuit under test 3 in parallel. Here, the result signal output in parallel from the circuit under test 3 is converted into serial data by a parallel-to-serial conversion circuit via the selector 4, and is output from the test result output/input terminal 18.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は被試験回路への入力部、又
は出力部又はその双方にパラレル・シリアル変換回路、
シリアル・パラレル変換回路を挿入することにより、集
積回路内部の試験用として使用する端子数を削減できる
効果がある。!たこの効果によシ、集積回路内部の複数
の被試験回路を同時に独立して試験することができる効
果がある。
As explained above, the present invention provides a parallel-to-serial conversion circuit at the input section, output section, or both of the circuit under test.
Inserting a serial-parallel conversion circuit has the effect of reducing the number of terminals used for testing inside the integrated circuit. ! The octopus effect has the advantage that a plurality of circuits under test within an integrated circuit can be simultaneously and independently tested.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の内部特定部分試験機構を有する集積回
路の構成図、第2図は従来の内部特定部分試験機構を有
する集積回路、第3図は内部特定部分試験機構を有しな
い集積回路の構成図である。 1・・・・・・集積回路、2・・・・・・内部回路、3
・・・・・・被試験回路、4・・・・・・セレクタ、5
・・・・・・シリアル・パラレル変換回路、6・・・・
・・パラレル・シリアル変換回路、10・・・・・・出
力専用端子、11・・・・・・入力専用端子、13・・
・・・・制御信号入力端子、15.16・・・・・・双
方向端子、17・・・・・・試験信号入力兼出力端子、
18・・・・・・試験結果出力兼入力端子。 情2図 fイ 第3図
Fig. 1 is a block diagram of an integrated circuit having a specific internal part testing mechanism according to the present invention, Fig. 2 is an integrated circuit having a conventional internal specific part testing mechanism, and Fig. 3 is an integrated circuit without a specific internal part testing mechanism. FIG. 1...Integrated circuit, 2...Internal circuit, 3
...Circuit under test, 4...Selector, 5
・・・・・・Serial-to-parallel conversion circuit, 6...
...Parallel-serial conversion circuit, 10...Output-only terminal, 11...Input-only terminal, 13...
... Control signal input terminal, 15.16 ... Bidirectional terminal, 17 ... Test signal input and output terminal,
18...Test result output and input terminal. Information Figure 2 f A Figure 3

Claims (1)

【特許請求の範囲】[Claims] 集積回路内部の特定部分の機能試験を目的として集積回
路内部の試験信号の入力部にシリアルパラレル変換回路
を含む。または試験信号の出力パラレル・シリアル変換
回路を通して出力される回路を含むことを特徴とする集
積回路。
A serial-to-parallel conversion circuit is included at the input section of the test signal inside the integrated circuit for the purpose of functional testing of a specific part inside the integrated circuit. Or an integrated circuit characterized by including a circuit that outputs a test signal through an output parallel-to-serial conversion circuit.
JP61158254A 1986-07-04 1986-07-04 Integrated circuit Pending JPS6314445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61158254A JPS6314445A (en) 1986-07-04 1986-07-04 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61158254A JPS6314445A (en) 1986-07-04 1986-07-04 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS6314445A true JPS6314445A (en) 1988-01-21

Family

ID=15667607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61158254A Pending JPS6314445A (en) 1986-07-04 1986-07-04 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS6314445A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370176A (en) * 1986-09-11 1988-03-30 Sony Corp Ic circuit
JPH01257344A (en) * 1988-04-07 1989-10-13 Nec Corp Semiconductor integrated circuit
JPH02101770A (en) * 1988-10-08 1990-04-13 Sharp Corp Integrated circuit
JPH0317577A (en) * 1989-06-14 1991-01-25 Matsushita Electron Corp Test circuit of semiconductor integrated circuit apparatus
JP2008310389A (en) * 2007-06-12 2008-12-25 Omron Corp Io unit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6018780A (en) * 1983-07-13 1985-01-30 Hitachi Ltd Inspecting apparatus
JPS60242380A (en) * 1984-05-16 1985-12-02 Hitachi Ltd Facilitating circuit for fault diagnosis of integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6018780A (en) * 1983-07-13 1985-01-30 Hitachi Ltd Inspecting apparatus
JPS60242380A (en) * 1984-05-16 1985-12-02 Hitachi Ltd Facilitating circuit for fault diagnosis of integrated circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370176A (en) * 1986-09-11 1988-03-30 Sony Corp Ic circuit
JPH01257344A (en) * 1988-04-07 1989-10-13 Nec Corp Semiconductor integrated circuit
JPH02101770A (en) * 1988-10-08 1990-04-13 Sharp Corp Integrated circuit
JPH0317577A (en) * 1989-06-14 1991-01-25 Matsushita Electron Corp Test circuit of semiconductor integrated circuit apparatus
JP2008310389A (en) * 2007-06-12 2008-12-25 Omron Corp Io unit

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