JPS60241245A - Semiconductor device and lead frame used therefor - Google Patents
Semiconductor device and lead frame used thereforInfo
- Publication number
- JPS60241245A JPS60241245A JP59096537A JP9653784A JPS60241245A JP S60241245 A JPS60241245 A JP S60241245A JP 59096537 A JP59096537 A JP 59096537A JP 9653784 A JP9653784 A JP 9653784A JP S60241245 A JPS60241245 A JP S60241245A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- lead
- leads
- series
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明り半導体装置、特に多数の外部接続端子を有する
半導体集積回路に適用して有効な技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique effective when applied to a semiconductor device, particularly a semiconductor integrated circuit having a large number of external connection terminals.
特開昭５５−３４４５３ 号にも記載されている如く、
半導体集積回路（以下においてＩＣという）の外部接続
端子は４０ビン、４２ビン等ピン数が増加し多ピン化の
傾向にある。このように外部接続端子数が増加すると、
ＩＣ内においてインナーリード間、及びタブ吊シリード
とインナリード間の距離が極めて躾まくなり、更にイン
ナーリードの先端が先細りの形状になるためワイヤーポ
ンディングが正確にできないという問題があることがわ
かった。As described in JP-A No. 55-34453,
The number of external connection terminals of semiconductor integrated circuits (hereinafter referred to as IC) is increasing, such as 40 bins, 42 bins, etc., and there is a trend toward multi-pins. As the number of external connection terminals increases in this way,
It was found that within the IC, the distance between the inner leads and between the tab suspension series lead and the inner lead became extremely tight, and furthermore, the tip of the inner lead became tapered, making it impossible to perform wire bonding accurately. .
更に、本発明者が検討したところによると、タブの形状
が大きく、パッケージの形状が大きい特に多ビン系のＩ
Ｃでは、タブ吊９リードが長くなるため、りブ吊シリー
ドのねじれによシタツブ自体の位置が変動する確率が大
きくなり、タブとインナーリードとが短絡して不良とな
ることが明らかになったＯ
また、インナーリード間の距離が狭まくなり、しかもそ
の先端部が先細シの形状であるため変形しやすく＠接す
るインナーリードが短絡する恐れがある。さらにワイヤ
ボンディング後のモールド時にワイヤーに流れが生じた
場合、上記ワイヤーが隣接す°るインナーリードに接触
する危険性があることも明らかになった。Furthermore, according to the inventor's study, it has been found that the tab shape is large and the package shape is large, especially for multi-bin type I.
In C, since the tab suspension lead 9 is longer, there is a greater probability that the position of the tab itself will change due to twisting of the rib suspension series lead, resulting in a short circuit between the tab and the inner lead, resulting in a failure. In addition, the distance between the inner leads becomes narrower, and since the tips thereof have a tapered shape, they are easily deformed and there is a risk of short-circuiting of the inner leads that are in contact with each other. Furthermore, it has been revealed that if the wire flows during molding after wire bonding, there is a risk that the wire will come into contact with the adjacent inner lead.
本発明は上述の如き技術的検討の結果なされたものでｓ
ｂ、その目的とするところは、タブ及びタブ品りリード
とインナーリードとの短絡、更にインナリード間の短絡
、及びモールド時におけるワイヤー流れによる短絡を防
止し、高信頼性の半導体装置を提供することにある０
本発明の上記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
◇
〔発明の概要〕
本願において開示きれる発明の概要ケ簡単に述べれば、
下記のとおシでりる〇
すなわち、タフ吊りリードの例えばインナリードの先端
部に近い位置、或いは全体に絶縁物を塗布するとともに
、タブの上面等にも絶縁物を塗布し、更にインナーリー
ドの例えば先端部やボンディング位置の後部等に絶縁物
を塗布し、タブ吊シリードとインナリードとの短絡、ｌ
ｌＪ接するインナリード相互の短絡、インナリードとボ
ンディングワイヤーとの短絡、タブ吊シリードとボンデ
ィングワイヤーとの短絡等を防止し、半導体集積回路の
信頼性を向上させるという本発明の目的を達成するもの
である。The present invention was made as a result of the above-mentioned technical studies.
b. The purpose is to prevent short circuits between tabs and tab product leads and inner leads, short circuits between inner leads, and short circuits due to wire flow during molding, and provide a highly reliable semiconductor device. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Ba,
In other words, apply an insulator to the tough hanging lead near the tip of the inner lead, or the entire area, and also apply an insulator to the top surface of the tab, etc. For example, apply an insulator to the tip or the rear of the bonding position to prevent short-circuiting between the tab hanging series lead and the inner lead.
The purpose of the present invention is to prevent short circuits between inner leads that are in contact with each other, short circuits between inner leads and bonding wires, short circuits between tab suspension series leads and bonding wires, and improve the reliability of semiconductor integrated circuits. be.
〔実施例−１〕
次に、本発明を適用した半導体装置の第１実施例を第１
図〜第３図を参照して説明する。なお、第１図はＩＣの
内部構造の要部を示す平面図であり、第２図は要部の斜
視図を示し、第３図は第２図のＡ−Ａ’断面図である〇
第１図に示すように、一対のタブ吊ブリード５０ａ 、
５０ｂによってタブ５１が保持され、その上部には半導
体チップ１００が接合されている。[Example-1] Next, a first example of a semiconductor device to which the present invention is applied will be described.
This will be explained with reference to FIGS. Note that Fig. 1 is a plan view showing the main parts of the internal structure of the IC, Fig. 2 is a perspective view of the main parts, and Fig. 3 is a sectional view taken along line AA' in Fig. 2. As shown in Figure 1, a pair of tab suspension bleeds 50a,
The tab 51 is held by the tab 50b, and the semiconductor chip 100 is bonded to the top of the tab 51.
そして、タブ５１の周囲には各インナーリード１〜４２
が設けられ、上記半導体チップ１００の上面に設けられ
たポンディングパッド１０１と上記インナーリード１〜
４２の先端とは、Ａｕ線１０２等によシ実緋で示す如く
ワイヤーボンディングされている。Each inner lead 1 to 42 is provided around the tab 51.
are provided, and a bonding pad 101 provided on the upper surface of the semiconductor chip 100 and the inner leads 1 to 1 are provided.
The tip of 42 is wire-bonded to Au wire 102 or the like as shown in red.
本実施例においては、タブ吊シリード５０ａ。In this embodiment, the tab hanging series lead 50a.
５０ｂとこれに隣接するインナーリードとの短絡を防止
するため、タブ早シリード５０ａ 、５０ｂの最もイン
ナリードと短絡し易い位置に絶縁物５２がコーティング
されている。この結果、タブ品りリード５０ａ 、５０
ｂの要部の外周囲は絶縁物５２によって７Ｍ３図に示す
如く完全に被ふくされ、隣接するインナーリード、Ａｕ
線１０２との短縮全防止することができる。In order to prevent a short circuit between the tab lead 50b and an adjacent inner lead, an insulating material 52 is coated on the tab early series leads 50a and 50b at a position where the short circuit with the inner lead is most likely to occur. As a result, tab product leads 50a, 50
The outer periphery of the main part b is completely covered with an insulator 52 as shown in Figure 7M3, and the adjacent inner lead, Au
Shortening of the line 102 can be completely prevented.
なお、上記絶縁物５２は、例えばポリイミド系樹脂が好
適である。すなわち、ポリイミド系樹脂はレジンとの密
着性が良好である。従って、レジンモールドを施こすこ
とにょυ、上記絶縁物５２とレジンが密層して、タフ゛
吊シリード５０ ａ ＊５０ｂを伝わって浸入しようと
する水分を阻止することができ、上記短絡防止と耐水性
の向上という二つの効果が得られる。更に、タブ吊りリ
ード５０ａ ＊ ５０ｂ ＋タブ５１と、絶縁物５２と
の熱膨張率が異なるため、タブ吊りリード５０ａ 。Note that the insulator 52 is preferably made of polyimide resin, for example. That is, polyimide resin has good adhesion to resin. Therefore, by applying the resin mold, the insulating material 52 and the resin form a dense layer, which can prevent moisture from entering through the tough hanging series leads 50a * 50b, thereby preventing short circuits and providing water resistance. Two effects can be obtained: improved sexual performance. Furthermore, since the tab suspension leads 50a*50b+tab 51 and the insulator 52 have different coefficients of thermal expansion, the tab suspension leads 50a.
５０ｂ、タブ５１が熱によ＃）＃張しようとしても絶縁
物５２によって押えられ、熱に対する機械的強度が向上
する。これにょシ、ボンディングの自由度が大幅に向上
するという効果が得られる。50b, even if the tab 51 tries to stretch due to heat, it is held down by the insulator 52, improving mechanical strength against heat. This has the effect that the degree of freedom in bonding is greatly improved.
〔実施例−２〕
次に、第４図を参照して本発明の第２実施例を説明する
。なお、上記第２実施例と同一の部分には同一の符号を
付し、その説明全省略する。[Embodiment 2] Next, a second embodiment of the present invention will be described with reference to FIG. Incidentally, the same parts as in the second embodiment are given the same reference numerals, and a complete explanation thereof will be omitted.
第４図に示すように、一対のタブ吊ｂｖ−ド５０ａ、５
０ｂの全体について絶縁物５２がコーティングされてい
る。この方法は、デュアルインライン型のＩＣの如く、
タブ吊シリード及びこれに瞬接するインナーリードが長
くなる場合に、特に有効である。As shown in FIG.
The entirety of 0b is coated with an insulator 52. This method is similar to a dual inline type IC.
This is particularly effective when the tab hanging series lead and the inner lead that momentarily contacts it are long.
そして、絶好物５２にポリイミド系樹月αを用いること
により、上記第１実施例と同様の効果が得られる。By using the polyimide-based tree α as the material 52, the same effects as in the first embodiment can be obtained.
〔実施例−３〕
次に、第５図を参照して本発明の第３実施例全説明する
。なお、本実施例においては、Ａｕ線１０２の一部図示
全省略する。[Embodiment 3] Next, a third embodiment of the present invention will be fully explained with reference to FIG. In this embodiment, a part of the Au wire 102 is completely omitted from illustration.
第５図に示すように、本実施例においては一対のタブｔ
ｉ＃）リード５０ａ１５０ｂ、タブ５１が例えばエポキ
シ側屈の如き合成樹脂によって一体に構成されている。As shown in FIG. 5, in this embodiment, a pair of tabs t
i#) The leads 50a and 150b and the tab 51 are integrally made of synthetic resin such as epoxy lateral bending.
これは低消費電力化が進み、一部のＩＣで放熱板として
タブを設ける必要の無いもめがあり、このような場合に
本実施例は有効である。なお、この場合は外部接続端子
にＧＮＤピンを設け、電気的にＧＮＤ電位を保持するこ
とができる。本実施例においても、前記実施例同様一対
のタブ吊りリード５０ａ 、５０ｂと隣接するインナー
リード、或いはＡｕ線１０２とが接触しても何等の問題
もない。This is due to the progress in reducing power consumption, and there is a problem that it is not necessary to provide a tab as a heat sink in some ICs, and this embodiment is effective in such cases. Note that in this case, a GND pin can be provided as an external connection terminal to electrically maintain the GND potential. In this embodiment, as in the previous embodiment, there is no problem even if the pair of tab suspension leads 50a, 50b come into contact with the adjacent inner lead or the Au wire 102.
ここでさらに注目すべきは、タフ゛吊シリード５０ａ、
＋５０ｂ＋タブ５１が全てエポキシ系樹脂により形成さ
れているだめ、エポキシ系樹脂により封止を行なえば、
封止後はそれらの樹脂が一体となシ、タブ吊りリード５
０ａ 、５０ｂと封止材との境界がなくな９、タブ吊り
リードからの水の浸入径路が断たれ、耐湿性の向上４８
計れるという効果が得られる。What should be further noted here is the tough suspension series 50a,
+50b+Tab 51 is all made of epoxy resin, so if it is sealed with epoxy resin,
After sealing, these resins are integrated, and the tab suspension lead 5
There is no boundary between 0a, 50b and the sealing material9, and the path of water intrusion from the tab hanging lead is cut off, improving moisture resistance48
The effect of being measurable can be obtained.
〔実施例−４〕
次に、第６ （ａ） 、 （ｂ）図を参照して本発明の
第４実施例を説明する。[Embodiment 4] Next, a fourth embodiment of the present invention will be described with reference to FIGS. 6(a) and 6(b).
第６図に示すように、本実施例においては各インナーリ
ード１〜４２の先端部に絶線物６０をコーティングした
ものである。このように構成することにより、隣接する
インナーリード間の先端部の短絡を防止することができ
、更にタブ吊シリード５０ａ 、５０ｂと隣接するイン
ナーリードとの短絡、Ａｕ線１０２とインナーリードの
先端部との短絡を防止することができる。As shown in FIG. 6, in this embodiment, the tips of each of the inner leads 1 to 42 are coated with a disconnected wire material 60. With this configuration, it is possible to prevent short-circuits at the tips of adjacent inner leads, and also prevent short-circuits between the tab hanging series leads 50a and 50b and the adjacent inner leads, and short-circuits between the Au wire 102 and the tips of the inner leads. This can prevent short circuits.
〔実施例−５〕
次に、第７ （ａ） 、 （ｂ）図を参照して本発明の
第５実施例を説明する。第７図に示すように、本実施例
においては各インナーリードｌ〜４２の先端部が合成樹
脂６１で構成されている。この場合も、上記第４実施例
と同様の効果が得られる。[Embodiment 5] Next, a fifth embodiment of the present invention will be described with reference to FIGS. 7(a) and 7(b). As shown in FIG. 7, in this embodiment, the tips of each of the inner leads 1 to 42 are made of synthetic resin 61. In this case as well, the same effects as in the fourth embodiment can be obtained.
〔実施例−６〕
次に、第８図を参照して本発明の第６笑施例を説明する
。第８図に示すように、本実施例においては各インナー
リード１〜４２の先端部とワイヤーボンディング位置の
後部とが絶線物６０．６２によりコーティングされてい
るＯこの場合、絶縁物６０は各インナーリード１〜４２
の先端部の短絡防止を行ない、絶縁物６２は各インナー
リード１〜４２を伝わって浸入しようとする水分を防止
する。また、絶Ａホ物６．０ 、６２に上記ポリイミド
系の合成樹脂を用いることによシ、レジンモールドの際
に絶縁物６０．６２とレジンとが密着し、各インナーリ
ード１〜４２の機械的強度が向上する０
〔実施例−７〕
次に、第９図を参照して本発明の第７実施例を説明する
。[Embodiment 6] Next, a sixth embodiment of the present invention will be described with reference to FIG. As shown in FIG. 8, in this embodiment, the tip of each inner lead 1 to 42 and the rear part of the wire bonding position are coated with an insulator 60, 62. Inner lead 1-42
The insulator 62 prevents moisture from entering through each of the inner leads 1 to 42. In addition, by using the above-mentioned polyimide-based synthetic resin for the absolute A-holes 6.0 and 62, the insulators 60 and 62 and the resin are in close contact with each other during resin molding. [Embodiment 7] Next, a seventh embodiment of the present invention will be described with reference to FIG. 9.
第８図に示すように、本実施例においては咎インナーリ
ード１〜４２の先端部に絶縁物６０をコーティングし、
更に一対のタブ吊りリード５０ａ。As shown in FIG. 8, in this embodiment, the tips of the inner leads 1 to 42 are coated with an insulator 60,
Furthermore, a pair of tab suspension leads 50a.
５０ｂとタブ５１の上面の外周囲とが絶縁物５２によっ
てコーティングされている。なお、絶イγ物５２．６０
はともにポリイミド系の合成樹脂が用いられる。注目す
べきは、一対のタブ吊りリード５０ａ 、５０ｂと隣接
するインナーリードとの短絡防止、各インナーリード間
の短絡防止、Ａｕ線１０２と他のインナーリードの先端
部品との短絡防止、Ａｕ１１０２とタブ５１との短絡防
止が行われているということである。また、一対のタブ
吊シリード５０ａ 、５０ｂに絶縁物５２をコーティン
グすることにより、レジンモールドしたとき両者の密着
が良好になシ、耐水性が向上するとともに、熱に対する
機械的強朋も向上する。50b and the outer periphery of the upper surface of the tab 51 are coated with an insulator 52. In addition, the absolute best item 52.60
Both are made of polyimide-based synthetic resin. What should be noted is the prevention of short circuits between the pair of tab suspension leads 50a and 50b and the adjacent inner leads, the prevention of short circuits between each inner lead, the prevention of short circuits between the Au wire 102 and the tip parts of other inner leads, and the prevention of short circuits between the Au 1102 and the tabs. This means that short circuits with 51 are prevented. Further, by coating the pair of tab suspension series leads 50a and 50b with the insulating material 52, when resin molding is performed, the adhesion between the two is good, and water resistance is improved, as well as mechanical strength against heat.
（１）一対のタブ品シリードとタブ、インナーリードの
ワイヤボンディング位置以外の位置に絶縁物をコーティ
ングすることにより、タブ吊りリードとの短絡、インナ
ーリード相互間の短絡、ワイヤーとタブ吊シリードとの
短絡、ワイヤーとインナーリードとの短絡が防止でき、
半Ｎｉ体装１ｉ７（の信頼性を向上させることができる
〇
（２）上ｄ己（１）によシ、りブ吊シリードとインナー
リードとを伝わる水の浸入を防止することができ、半導
体装置の耐水性を向上させることができる。(1) By coating a pair of tab product series leads, tabs, and inner leads with insulators at positions other than the wire bonding positions, short circuits with the tab suspension leads, shorts between inner leads, and wires and tab suspension series leads can be prevented. Prevents short circuits and short circuits between the wire and the inner lead.
The reliability of the half-Ni housing 1i7 can be improved (2) The upper part (1) can prevent water from entering through the rib suspension series lead and the inner lead, and the semiconductor The water resistance of the device can be improved.
（３）上記（１）により、ＩＣの発熱又は加熱によるタ
ブ吊りリード、タブ、インナリードの変形が熱膨張の異
なる絶縁物によって防止されるため、半導体装置の信頼
性を向上させることができる。(3) According to (1) above, the deformation of the tab suspension lead, tab, and inner lead due to heat generation or heating of the IC is prevented by the insulators having different thermal expansions, so that the reliability of the semiconductor device can be improved.
（４） 上記（１）より歩留シの向上が計れる。(4) From (1) above, the yield can be improved.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その襞旨を逸脱しない範囲で糊々変更可
能であることはいうまでもない０
例えは、タブ吊りリード、タブを第７実施例の如く構成
し、インナーリードを第６″Ｊ：施例のように構成して
もよい。Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above-mentioned examples, and it is understood that changes can be made without departing from the spirit of the invention. Needless to say, 0. For example, the tab suspension lead and the tab may be configured as in the seventh embodiment, and the inner lead may be configured as in the 6th"J: embodiment.
また、タブ吊シリード、タグを第３実施例の如く構成し
、インナーリードを第６実施例の如くに構成してもよい
。Further, the tab hanging series lead and the tag may be constructed as in the third embodiment, and the inner lead may be constructed as in the sixth embodiment.
上記各変形例の何れであっても、上記効果が得られる。The above effects can be obtained in any of the above modifications.
以上の説明では、主として本発明者によってなされた発
明をその背景となった利用分野である半導体装置につい
て説明したが、上記それに限定されるものではない。In the above description, the invention made by the present inventor has mainly been described with respect to a semiconductor device, which is the application field that is the background of the invention, but the invention is not limited thereto.
本発明は、多数の外部接続端子を冶する半導体集積回路
全般に利用することかできる。The present invention can be used in general semiconductor integrated circuits that provide a large number of external connection terminals.
第１図は本発明を適用した半導体装置の第１実施例を示
すＩＣの要部の平面図を示し、第２図は上記ＩＣの要部
の斜視図を示し、第３図は上記第２図のＡ −Ａ 断面
図を示し、第４図は本発明の第２実施例を示すＩＣの要
部の平面図を示し、
紀５図は不発つｊの第３実施例を示すＩＣの要部の平面
図を示し、
第６（ａ）図は本発明の第４実施例を示すＩＣｌ１７）
要部の平面図を示し、
第６６）図は本発明の第４笑施例を示１■Ｃの要。
部の斜視図を示し、
第７（ａ）図は本発明の第５実施例を示すＩＣの要部の
平面図を示し、
第７６）図は本発明の第５実施例を示すＩＣの要部の断
面図を示し、
第８１．！！、Ｉは本発明の第６実施例を示すＩＣの要
部の平面図を示し、
第９図は本発明の第７実施例を示すＩＣの要部の平面は
１を示す。
１〜４２・・・インナーリード、５０ ａ ＊ ｂ Ｏ
ｂ・・・りブ吊りリード、５１・・・タフ゛、５２，６
θ、６２・・・絶嫌物、１００・・・半導体チップ、１
０１・・・ボン第 １ 図
−
ト
）−
０１
第 ５ 図
６０ｂ
第 ６ 図
第 ７ 図
（１１）
（ｂ）
第 ８ 図
ｂFIG. 1 shows a plan view of the main parts of an IC showing a first embodiment of the semiconductor device to which the present invention is applied, FIG. 2 shows a perspective view of the main parts of the above IC, and FIG. 3 shows the above second embodiment. 4 shows a plan view of the main parts of the IC showing the second embodiment of the present invention, and Fig. 5 shows the main parts of the IC showing the third embodiment of the unexploded j. FIG. 6(a) shows a fourth embodiment of the present invention.
Fig. 66) shows the fourth embodiment of the present invention, and shows the main part of 1C. FIG. 7(a) is a plan view of main parts of an IC showing a fifth embodiment of the present invention, and FIG. 76) is a perspective view of main parts of an IC showing a fifth embodiment of the present invention. 81. shows a cross-sectional view of the section; ! ! , I shows a plan view of the main part of an IC showing a sixth embodiment of the present invention, and FIG. 9 shows a plan view of the main part of an IC showing a seventh embodiment of the invention. 1 to 42... Inner lead, 50 a * b O
b... Rib suspension lead, 51... Tough, 52, 6
θ, 62... Detestable thing, 100... Semiconductor chip, 1
01...Bon Fig. 1 - g) - 01 Fig. 5 Fig. 60b Fig. 6 Fig. 7 (11) (b) Fig. 8 b
Claims (1)
対のタブ吊シリードと、前記半導体チップ表面のポンデ
ィングパッドと電気的に接続されるリードを有する半導
体装置であって、リードの少なくとも先端部分及び又は
、少なくともタブ吊シリードのリード先端近傍部分に納
材Ｉ−を有していることを特徴とする半導体装置。 ２、半導体チップを保持するタブと、タブを保持する一
対のタブ吊りリードと、前記半導体チップ表面のポンデ
ィングパッドと金ワイヤを介して電気的に接続きれるリ
ードを有するリードフレームであって、リードの少なく
とも先端部分、及び又は、少なくともタブｔ１１シリー
ドのリード先端近傍部分に絶蘇層を有していることを特
徴とするリードフレーム。[Claims] 1. A semiconductor device having a tab for holding a semiconductor chip, a pair of tab hanging series leads for holding the tab, and a lead electrically connected to a bonding pad on the surface of the semiconductor chip, 1. A semiconductor device having a delivery material I- at least at the tip end of the lead and/or at least at a portion near the lead tip of the tab-hanging series lead. 2. A lead frame having a tab that holds a semiconductor chip, a pair of tab suspension leads that hold the tab, and a lead that can be electrically connected to a bonding pad on the surface of the semiconductor chip via a gold wire, the lead 1. A lead frame comprising a resuscitation layer on at least a tip end portion of the tab t11 series lead and/or at least a portion near the lead tip of the tab t11 series lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59096537A JPS60241245A (en) | 1984-05-16 | 1984-05-16 | Semiconductor device and lead frame used therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59096537A JPS60241245A (en) | 1984-05-16 | 1984-05-16 | Semiconductor device and lead frame used therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60241245A true JPS60241245A (en) | 1985-11-30 |
Family
ID=14167861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59096537A Pending JPS60241245A (en) | 1984-05-16 | 1984-05-16 | Semiconductor device and lead frame used therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60241245A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63177061U (en) * | 1987-04-24 | 1988-11-16 | ||
| JP2012151511A (en) * | 2012-05-15 | 2012-08-09 | Mitsubishi Electric Corp | Resin sealing type semiconductor device |
-
1984
- 1984-05-16 JP JP59096537A patent/JPS60241245A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63177061U (en) * | 1987-04-24 | 1988-11-16 | ||
| JP2012151511A (en) * | 2012-05-15 | 2012-08-09 | Mitsubishi Electric Corp | Resin sealing type semiconductor device |
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