JPS6024031A - Semiconductor wafer prober - Google Patents

Semiconductor wafer prober

Info

Publication number
JPS6024031A
JPS6024031A JP13218083A JP13218083A JPS6024031A JP S6024031 A JPS6024031 A JP S6024031A JP 13218083 A JP13218083 A JP 13218083A JP 13218083 A JP13218083 A JP 13218083A JP S6024031 A JPS6024031 A JP S6024031A
Authority
JP
Japan
Prior art keywords
wafer
defective
chip
mark
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13218083A
Other languages
Japanese (ja)
Other versions
JPH0441496B2 (en
Inventor
Junichi Inoue
準一 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TELMEC CO Ltd
Original Assignee
TELMEC CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TELMEC CO Ltd filed Critical TELMEC CO Ltd
Priority to JP13218083A priority Critical patent/JPS6024031A/en
Publication of JPS6024031A publication Critical patent/JPS6024031A/en
Publication of JPH0441496B2 publication Critical patent/JPH0441496B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

PURPOSE:To enable to automatically inspect the addition of defective marks to defective chips by a method wherein the result of quality judgement of each wafer chip is stored to a wafer map, and the defective mark is recognized by a recognition device. CONSTITUTION:The electric characteristics of a wafer chip are measured by contact of a probe card needle with a chip pad on the wafer positioned at a fixed position. The quality is judged from the measured result of electrical characteristics obtained. Then, the defective mark is added to the wafer chip judged as defective by a defective signal from a tester. Thereafter, the shape of defective marks added to this wafer is recognized by the recognition device, and the measured result of wafer chips in the wafer is stored as the wafer map. Next, the shape of defective marks recognized by the device is compared with that measured; it is judged as a defective wafer chip in the case of agreement. Finally, the omission of defective mark puncing to the defective wafer chips is discovered from the stored result in the wafer map, and then a defective mark is added again to this chip.

Description

【発明の詳細な説明】 この発明は半導体ウェハ製造工程における半導体ウェハ
測定装置、特に半導体ウエハプローバに関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor wafer measuring device used in a semiconductor wafer manufacturing process, and particularly to a semiconductor wafer prober.

従来の半導体ウェハチップは、通常1枚のウェハ上に数
百側同時に形成され、測定終了後に個々に切り離される
。分割されたチップのうち、良品のチップのみ取り出し
パッケージングして集積回路(IC)製品が完成する。
Conventional semiconductor wafer chips are usually formed on several hundred sides on one wafer at the same time, and are individually separated after measurement. Of the divided chips, only good chips are taken out and packaged to complete an integrated circuit (IC) product.

これをもう少し詳しく述べると、ウェハ内のチップの電
気的特性を測定する工程では、チップの良品と不良品を
判断する通常テスターと称される装置からチップへ入力
信号を送り、テスターはチップからの出力信号を受けて
その出力信号を判断し、チップが良品であるか不良品で
あるかを判断する。
To explain this in more detail, in the process of measuring the electrical characteristics of chips within a wafer, an input signal is sent to the chip from a device called a tester, which determines whether the chip is good or bad. It receives the output signal and judges the output signal to determine whether the chip is a good product or a defective product.

通常上記の入出力信号は、チップに設けられた電極(以
下パッドと称する)の位置に合うようプローブカードに
配置された触針(以下プローブカード針と称する)によ
ってテスターから送出され、またはテスターへ送り込ま
れる。テスターは、チップからの信号を受けて良品であ
るか不良品であるかを判断し、不良品の場合は半導体ウ
エハプローバへ不良信号を発信する。半導体ウエハプロ
ーバは、上記の不良信号に従ってチップ表面にマークを
付けるインカー(マーカー)と称する装置を作動し、不
良ウェハチップの表面にマークを付加する。
Normally, the above input/output signals are sent from the tester or sent to the tester by a stylus (hereinafter referred to as probe card needle) placed on the probe card to match the position of the electrode (hereinafter referred to as pad) provided on the chip. sent. The tester receives a signal from the chip and determines whether it is a good product or a defective product, and if it is a defective product, sends a defect signal to the semiconductor wafer prober. A semiconductor wafer prober operates a device called an inker (marker) that marks the surface of a chip according to the above-mentioned defect signal, and adds a mark to the surface of a defective wafer chip.

従来このようなインカーは、半導体ウエハプローバの中
央に1個もしくは複数個の針部が設けられたものである
。その際、テスターが不良品と判断したチップ表面にマ
ークを付加する動作は、第1に、1個のチップの測定を
した時に直ちに行う場合と、第2に、不良品と判断した
チップを地図化(以下マツピングと称する)1.、て記
憶領域(以下ウェハマツプと称する)に記憶しておき、
すべてのチップの測定が終了した時に改めて別の場所で
、不良品と判断されたチップにまとめてマーキングを行
う場合とがある。
Conventionally, such an inker has one or more needles provided in the center of a semiconductor wafer prober. In this case, the tester adds a mark to the surface of a chip judged to be defective in two ways: firstly, it is done immediately after measuring a single chip, and secondly, the tester adds a mark to the surface of a chip judged to be defective. (hereinafter referred to as mapping) 1. , and store it in a storage area (hereinafter referred to as wahammap),
When all the chips have been measured, chips that are determined to be defective may be marked again at another location.

また上述のインカーの機構としては、■針部によりイン
クをチップ表面に付着させる型式と。
The mechanism of the inker mentioned above is: (1) A type in which ink is attached to the chip surface using a needle.

■硬質の針でチップ表面を叩打して損傷を与える型式と
、■レーザー光をチップ表面に照射してチップ表面を溶
解させる型式とがある。
There are two types: (1) which damages the chip surface by hitting it with a hard needle, and (2) which melts the chip surface by irradiating the chip surface with laser light.

以上の3種類のマークを付加するいずれの型式において
も、マーキングの際にインカーが針部をチップに向かっ
て打っときは、半導体ウェハプローバの機能の一つとし
て電流が通って電磁石になるため、通電によるインカー
の動作が把握できる。しかしマークを実際に付加したが
否かまで確認していないので、■においてインクが切れ
た状態でインカーが作動した場合には、マークが付加さ
れていないことがある。そのため不良品のチップでも良
品と判断してしまう結果となる。また■の硬質の針でチ
ップ表面を叩打して損傷させる型長のものについても、
先端の針が折れてウェハチップまで届くことができない
時も、同様に不良品のチップでも良品と判断してしまう
。■のレーザー光をチップ表面に照射してチップ表面を
溶解させる型式の場合も同様で、レーザー光の発射さ九
る先端部の破損により、レーザー光が発射さ九ない場合
も生ずるのである。よってこれも不良品のチップでも良
品と判断してしまうのである。
In any of the above three types of marks, when the inker hits the needle toward the chip during marking, one of the functions of the semiconductor wafer prober is that current passes through it and it becomes an electromagnet. The operation of the inker when energized can be understood. However, since it is not confirmed whether the mark has actually been added or not, if the inker is activated when the ink runs out in (2), the mark may not have been added. As a result, even a defective chip is judged to be a good chip. In addition, regarding the long mold type (■) in which the chip surface is damaged by hitting it with a hard needle,
When the tip of the needle breaks and cannot reach the wafer chip, a defective chip is similarly judged to be a good chip. The same is true for the method (2) in which the chip surface is irradiated with laser light to melt the chip surface, and there are cases where the laser light is not emitted due to damage to the tip of the chip. Therefore, even a defective chip is judged to be good.

本発明の目的は、これらの問題点を解決するためにテス
ターにより不良ウェハチップと判断された時、この不良
ウェハチップがインカーで不良マークを付加しであるか
を、自動的に認識して確認することのできる半導体ウェ
ハプローバを提供することである。
In order to solve these problems, the purpose of the present invention is to automatically recognize and confirm whether or not the defective wafer chip is marked with a defective mark by an inker when the tester determines that the defective wafer chip is a defective wafer chip. An object of the present invention is to provide a semiconductor wafer prober that can perform the following steps.

以下本発明の一実施例を図面を用いて説明すると、第1
図はこの発明の半導体ウェハプローバの概要を示すブロ
ック図、第2図は半導体ウェハの表面を示す平面図、第
3図はウェハマツプ図である。
One embodiment of the present invention will be described below with reference to the drawings.
1 is a block diagram showing an outline of the semiconductor wafer prober of the present invention, FIG. 2 is a plan view showing the surface of a semiconductor wafer, and FIG. 3 is a wafer map diagram.

本発明における半導体ウェハプローバは、被測定物であ
る半導体ウェハを載置台に載置し真空吸着して固定する
。この載置台は水平のX軸、Y軸方向と、上下のY軸方
向に移動する駆動機構により自動操作される。所定位置
に位置決めされたウェハ上に、プローブカード針をチッ
プのパッド上番;接触させて測定する。このプローブカ
ード針は、テスターと接続してウェハの良、不良を測定
する測定機構を有している。このテスターは、半導体ウ
エハプローバの位置決め等の機構を通して個々のウェハ
チップを測定するもので、得られたウェハチップの電気
的特性の測定の結果により良、不良の判断をする判断機
能を持っている。
In the semiconductor wafer prober of the present invention, a semiconductor wafer, which is an object to be measured, is placed on a mounting table and fixed by vacuum suction. This mounting table is automatically operated by a drive mechanism that moves in the horizontal X- and Y-axis directions and in the vertical Y-axis direction. The probe card needle is brought into contact with the top pad of the chip on the wafer positioned at a predetermined position, and measurement is performed. This probe card needle has a measuring mechanism that connects to a tester and measures whether the wafer is good or bad. This tester measures individual wafer chips through a mechanism such as the positioning of a semiconductor wafer prober, and has a judgment function that determines whether the wafer chips are good or bad based on the results of measuring the electrical characteristics of the obtained wafer chips. .

このようにして判断されたテスターの測定の結果は、テ
スターからの不良信号によって不良マークを付加する、
マーキング機構によりウェハ上に表示される。その後、
このウェハに(=l加した、ウェハ全体としての不良マ
ーク形状を認識装置により認識するとともに、このウェ
ハ内のウェハチップの測定結果をウェハマツプとして記
憶する。このような各機構は全体として制御機構により
制御される。勿論個々の各機構自体はそれぞれ公知のも
のを使用することができる。
The result of the tester measurement determined in this way is marked with a defective mark by the defective signal from the tester.
It is displayed on the wafer by a marking mechanism. after that,
The recognition device recognizes the shape of the defect mark on the wafer as a whole (=l), and the measurement results of the wafer chips within this wafer are stored as a wafer map. Of course, each individual mechanism itself can be a known one.

この発明の半導体ウエハプローバにおいては。In the semiconductor wafer prober of this invention.

(D駆動機構におけるX軸、Y#力方向アドレス信号と
テスターによるチップの測定結果における良、不良の信
号とを、各チップとアドレスとを対応させた測定情報と
して、ウェハマツプと称する制御機構の記憶領域に記憶
させ、第2図のようにウェハ/内にある不良チップ8を
テスターの不良信号により表示して、X軸、Y軸方向の
アドレスにマツピングする。■上記ウェハマツプに記憶
されている情報をもとに、ウェハ内の不良ウェハチップ
表面にインカーを作動させて、マークを付加する。この
工程までは従来技術で行われる。
(The X-axis and Y# force direction address signals in the D drive mechanism and the good/bad signals in the chip measurement results by the tester are stored in a control mechanism called a wafer map as measurement information that associates each chip with an address.) As shown in Fig. 2, the defective chip 8 on the wafer is displayed by the defective signal of the tester and mapped to addresses in the X-axis and Y-axis directions.■ Information stored in the wafer map above. Based on this, an inker is operated on the surface of the defective wafer chip within the wafer to add a mark.Up to this step, conventional techniques are used.

なお、付加された不良マークを認識装置で認識させた場
合、その認識による情報は埃と間違える可能性があるの
で、先ずウェハプロービングが予め不良マークの形状を
記憶しておき、これを基本不良マークと呼ぶ。この基本
不良マークと付加された不良マークとを比較し、基本不
良マークに沿った形状であればテスターによる測定結果
に対応する不良ウェハチップであり、ウェハチップの表
面に不良マークが付加されていることが明確になる。ま
たこの不良マークは半導体ウエハプローバによるウェハ
内チップの測定以後に自動的に認識し、良品のウェハチ
ップのみ組立てる工程があるが、この場合も不良マーク
の大きさく面積のことをさす)により判定していること
が多いので、ウェハプロービングの工程において、不良
マークの大きさをも自動的に認識することは極めて有用
である。
Note that if the added defective mark is recognized by a recognition device, the information from the recognition may be mistaken for dust, so first, wafer probing memorizes the shape of the defective mark in advance and uses it as a basic defective mark. It is called. This basic defective mark is compared with the added defective mark, and if the shape is along the basic defective mark, it is a defective wafer chip that corresponds to the measurement result by the tester, and a defective mark has been added to the surface of the wafer chip. Things become clear. In addition, this defective mark is automatically recognized after the chips in the wafer are measured using a semiconductor wafer prober, and there is a process in which only good wafer chips are assembled. Therefore, it is extremely useful to automatically recognize the size of defective marks in the wafer probing process.

ここでウェハマツプの示す測定結果が不良ウェハチップ
であって、認識装置で認識した結果が不良マークが認識
されない場合は、再び不良信号によって不良ウェハチッ
プの表面に、不良マークが付加される。その後再び不良
マークを認識装置で認識させて、その結果不良マークが
認識さ九ることになる。
If the measurement result indicated by the wafer map is a defective wafer chip and the recognition device does not recognize a defective mark, a defective mark is added to the surface of the defective wafer chip again by the defective signal. Thereafter, the defective mark is recognized by the recognition device again, and as a result, the defective mark is recognized.

また上記の認識をすることができない状態が数回続くこ
とになると、例えばオペレータに報知する機能を取り付
けておけば、オペレータによるインク充填により常に不
良ウェハチップのみに不良マークを付加したことを確認
して、半導体ウエハプローバ全工程の仕事を終了する。
In addition, if the above-mentioned inability to recognize continues several times, for example, if a function is installed to notify the operator, the operator can always check that only defective wafer chips have been marked with defective chips by filling ink. Then, the entire process of the semiconductor wafer prober is completed.

この発明は以上のように構成されているため。This invention is configured as described above.

半導体ウェハの良品ウェハチップを除いてすべての不良
品ウェハチップに不良マークが付加されており、ウェハ
チップの選別時に不良マークを目印として選別作業を行
うので、半導体ウェハチップとして信頼性の高い品質の
製品が得られる。また自動化に際して非常に有効である
A defective mark is added to all defective wafer chips except for good semiconductor wafer chips, and since the defective mark is used as a guide when sorting wafer chips, the quality of semiconductor wafer chips is highly reliable. product is obtained. It is also very effective in automation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は1本発明の半導体ウエハプローバの一実施例を
示す概略ブロック図、第2図はウェハ表面の不良ウェハ
チップの例を示す平面図、第3図はウェハマツプを説明
するための概略図である。 /09.半導体ウェハ 810.不良ウエハチップ第1
図 第2図 第3図
FIG. 1 is a schematic block diagram showing an embodiment of a semiconductor wafer prober of the present invention, FIG. 2 is a plan view showing an example of a defective wafer chip on the wafer surface, and FIG. 3 is a schematic diagram for explaining a wafer happe. It is. /09. Semiconductor wafer 810. Defective wafer chip 1st
Figure 2 Figure 3

Claims (1)

【特許請求の範囲】 1、ウェハ上に配置されたウェハチップに、プローブカ
ード針を接触させて電気的特性を測定し、測定の結果に
より不良ウェハチップにはその表面に不良マークを付加
する半導体ウェハプローバにおいて、 ウェハの各ウェハチップの良、否を測定した結果をマツ
ピングし、これをウェハマツプに記憶するとともに、実
際に不良ウェハチップに付加した不良マークを認識装置
で認識し、前記ウェハマツプに記憶させた情報と、前記
認識装置で認識した情報との比較により、不良ウェハチ
ップへの不良マークの打ちもれを発見し、この打ちもれ
不良ウェハチップに再度不良マークを付して確認するこ
とを特徴とする半導体ウェハプローバ。
[Claims] 1. A semiconductor device in which electrical characteristics are measured by bringing a probe card needle into contact with wafer chips placed on a wafer, and defective marks are added to the surface of defective wafer chips based on the measurement results. The wafer prober maps the results of measuring whether each wafer chip on the wafer is good or not and stores it in the wafer map, and the recognition device recognizes the defect mark actually added to the defective wafer chip and stores it in the wafer map. By comparing the information detected by the recognition device with the information recognized by the recognition device, a defective mark is found on the defective wafer chip, and the defective mark is again attached to the defective wafer chip to confirm the defective mark. A semiconductor wafer prober featuring:
JP13218083A 1983-07-19 1983-07-19 Semiconductor wafer prober Granted JPS6024031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13218083A JPS6024031A (en) 1983-07-19 1983-07-19 Semiconductor wafer prober

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13218083A JPS6024031A (en) 1983-07-19 1983-07-19 Semiconductor wafer prober

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP13943393A Division JPH08274133A (en) 1993-05-18 1993-05-18 Semiconductor wafer prober

Publications (2)

Publication Number Publication Date
JPS6024031A true JPS6024031A (en) 1985-02-06
JPH0441496B2 JPH0441496B2 (en) 1992-07-08

Family

ID=15075249

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13218083A Granted JPS6024031A (en) 1983-07-19 1983-07-19 Semiconductor wafer prober

Country Status (1)

Country Link
JP (1) JPS6024031A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62224943A (en) * 1986-03-27 1987-10-02 Rohm Co Ltd Wafer prober
JPS63127545A (en) * 1986-11-17 1988-05-31 Tokyo Electron Ltd Prober
US4965515A (en) * 1986-10-15 1990-10-23 Tokyo Electron Limited Apparatus and method of testing a semiconductor wafer
JPH08274134A (en) * 1996-04-22 1996-10-18 Tokyo Electron Ltd Method for marking defective element
JPH08330367A (en) * 1995-05-31 1996-12-13 Nec Yamagata Ltd Apparatus for marking semiconductor wafer and its marking method
JP2019091773A (en) * 2017-11-14 2019-06-13 三菱電機株式会社 Semiconductor device evaluation apparatus and semiconductor device evaluation method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5717873A (en) * 1980-07-04 1982-01-29 Mitsubishi Electric Corp Inspection method of semiconductor element
JPS5818936A (en) * 1981-07-27 1983-02-03 Toshiba Corp Selecting system for semiconductor element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5717873A (en) * 1980-07-04 1982-01-29 Mitsubishi Electric Corp Inspection method of semiconductor element
JPS5818936A (en) * 1981-07-27 1983-02-03 Toshiba Corp Selecting system for semiconductor element

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62224943A (en) * 1986-03-27 1987-10-02 Rohm Co Ltd Wafer prober
US4965515A (en) * 1986-10-15 1990-10-23 Tokyo Electron Limited Apparatus and method of testing a semiconductor wafer
JPS63127545A (en) * 1986-11-17 1988-05-31 Tokyo Electron Ltd Prober
JPH08330367A (en) * 1995-05-31 1996-12-13 Nec Yamagata Ltd Apparatus for marking semiconductor wafer and its marking method
JPH08274134A (en) * 1996-04-22 1996-10-18 Tokyo Electron Ltd Method for marking defective element
JP2019091773A (en) * 2017-11-14 2019-06-13 三菱電機株式会社 Semiconductor device evaluation apparatus and semiconductor device evaluation method

Also Published As

Publication number Publication date
JPH0441496B2 (en) 1992-07-08

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