JPS60234334A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60234334A
JPS60234334A JP8942384A JP8942384A JPS60234334A JP S60234334 A JPS60234334 A JP S60234334A JP 8942384 A JP8942384 A JP 8942384A JP 8942384 A JP8942384 A JP 8942384A JP S60234334 A JPS60234334 A JP S60234334A
Authority
JP
Japan
Prior art keywords
semiconductor chip
mounting board
mounting substrate
wire
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8942384A
Other languages
Japanese (ja)
Inventor
Chiyoushirou Mizuno
水野 長市郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8942384A priority Critical patent/JPS60234334A/en
Publication of JPS60234334A publication Critical patent/JPS60234334A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected

Abstract

PURPOSE:To enable to secure an excellent heat radiating property and to enhance the reliability of a semiconductor chip by a method wherein the electric connection wire attached to the semiconductor chip is connected to a mounting substrate by bending it property and, at the same time, the semiconductor chip is bonded to the mounting substrate through the intermediary of a metal connecting member. CONSTITUTION:The conductive connection wire 2, one side of which is attached to the bonding pad 3 of a semiconductor chip 1, is bent along the side face of the semiconductor chip 1 isolated from the side face of the semiconductor chip, and the other end part positioned on the reverse side of the semiconductor chip is connected to the conductive part 5 which is multiple-arrangement patterned on a mounting substrate 4 using a connecting material 6. When said mounting substrate 4 is constituted by a material having excellent heat radiating property and the semiconductor chip 1 is constituted by a silicon substrate, the difference of thermal expansion coefficient of the connection part between the substrate 1 and the mounting substrate 4 can be absorbed by the elasticity of the connecting wire 2, and the trouble pertaining to the thermal distortion caused by the difference in thermal expansion coefficient of the connection part can be dissolved.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置に関し、特に、半導体チップの基板
への実装技術に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a technique for mounting a semiconductor chip onto a substrate.

〔背景技術〕[Background technology]

この方式は、半導体チップに形成された半球状に半田バ
ンプ電極により半導体チップをフェイスダウンボンディ
ングして実装基板に実装する方式しかるに、このフリッ
プチップ方式によれば、半導体チップが半田バンプによ
り実装基板から浮いている状態にあるので、半導体チッ
プから発した熱が逃げにくくその放熱性に制限がある。
In this flip-chip method, the semiconductor chip is face-down bonded to the mounting board using hemispherical solder bump electrodes formed on the semiconductor chip.However, according to this flip-chip method, the semiconductor chip is separated from the mounting board by solder bumps. Since it is in a floating state, it is difficult for the heat generated from the semiconductor chip to escape, and its heat dissipation is limited.

一方、このフリップチップ方式によれば、半導体チップ
(通常シリコン基板が使用される)と実装基板(通常セ
ラミック基板が使用される)との熱膨張係数差に基づく
熱ひずみが半田バンプに集中するため、半田バンプが熱
疲労限界に達すると、機械的、電気的に接続不良となる
On the other hand, according to this flip-chip method, thermal strain due to the difference in coefficient of thermal expansion between the semiconductor chip (usually a silicon substrate is used) and the mounting substrate (usually a ceramic substrate is used) concentrates on the solder bumps. When the solder bump reaches its thermal fatigue limit, mechanical and electrical connections will fail.

このようなことは、半導体装置の信頼性を著しく低下さ
せることになる。(フリップチップ方式については、た
とえば工業調査会発行rrc化実キ:キ唱唱幌雫慎」称
4I計戯陣≦母)沈裔彬;装技術」の8IPに示されて
いる。) 〔発明の目的〕 本発明は半導体チップの良好な放熱性を確保するととも
に半導体チップの実装基板との接続部の信頼性を確保し
、かつ、高密度実装、可能な半導体装置を提供すること
を目的としたものである。
This will significantly reduce the reliability of the semiconductor device. (The flip-chip method is shown, for example, in IP 8 of RRC ``Kisho Shohoro Shizushin'' published by the Industrial Research Association, ``4I Plans ≦ Mother) Shen Subin; Mounting Technology''. ) [Objective of the Invention] The present invention provides a semiconductor device that ensures good heat dissipation of a semiconductor chip, ensures reliability of the connection portion between the semiconductor chip and the mounting board, and enables high-density packaging. The purpose is to

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。
The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、半導体チップに電気的接続線を取付け、この
接続線を適宜折曲げ実装基板に接続するとともに、半導
体チップを金属製接続部材を介して実装基板にボンディ
ングするようにしたので、半導体チップの熱を前記接続
線および接続部材を介して実装基板に逃がす、二とがで
き、したがって、半導体チップの放熱性が良くかつ半導
体チップと実装基板間の熱膨張係数差は、その接続線に
吸収されるためその接続部の信頼性が向上し、さらに複
数の半導体チップを比較的狭い面積で配設できるため高
密度実装を可能としたものである。
In other words, electrical connection wires are attached to the semiconductor chip, and these connection wires are bent appropriately and connected to the mounting board, and the semiconductor chip is bonded to the mounting board via a metal connection member, so that the heat of the semiconductor chip is reduced. The heat dissipation of the semiconductor chip is good, and the difference in thermal expansion coefficient between the semiconductor chip and the mounting board is absorbed by the connection wire. Therefore, the reliability of the connection part is improved, and since a plurality of semiconductor chips can be arranged in a relatively narrow area, high-density packaging is possible.

〔実施例〕〔Example〕

次に、本発明の実施例を第1図および第2図により説明
する。
Next, an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

第1図は、本発明半導体装置の要部平面図、第2図は、
第1図1−T線に沿う断面図を示す。
FIG. 1 is a plan view of the main parts of the semiconductor device of the present invention, and FIG.
FIG. 1 shows a sectional view taken along line 1-T.

第1図にて、1は半導体チップで、例えばシリコン単結
晶基板から成る。周知の技術によって、この半導体チッ
プ内には多数の回路素子が形成され、1つの回路機能を
与えている。回路素子は、例えばMOSやバイポーラか
ら成り、これらの回路素子によって、例えば論理回路お
よびメモリ回路機能が形成されている。
In FIG. 1, numeral 1 denotes a semiconductor chip, which is made of, for example, a silicon single crystal substrate. By well-known techniques, a large number of circuit elements are formed within this semiconductor chip to provide a single circuit function. The circuit elements are made of, for example, MOS or bipolar, and these circuit elements form, for example, a logic circuit and a memory circuit function.

この四角形状の半導体チップ1上の周辺に適宜間隔をお
いて多数のストライプ状の電気的接続線2の一端部を接
続する。
One end portion of a large number of striped electrical connection lines 2 is connected to the periphery of the rectangular semiconductor chip 1 at appropriate intervals.

この接続は、例えば、半導体チップ1の周辺に多数配列
されたポンディングパッド3に前記接続線2をワイヤボ
ンディングと同様の方法例えば超音波ボンディング法に
より接続してもよいし、また、半導体チップにバンプ電
極を形成しておき、これをポリイミドフィルム(テープ
)上のフィンガーリードにボンディングするようなフィ
ルムキャリア方式により接続してもよい。
This connection may be made, for example, by connecting the connection wire 2 to a large number of bonding pads 3 arranged around the semiconductor chip 1 by a method similar to wire bonding, such as ultrasonic bonding, or by connecting the connection wire 2 to a large number of bonding pads 3 arranged around the semiconductor chip 1. Bump electrodes may be formed in advance and connected by a film carrier method such as bonding to finger leads on a polyimide film (tape).

ストライプ状の電気的接続線2は導電性の材料例えば金
属により構成される。金属の具体例としては、銅(Cu
)、アミニウム(AQ)があげられる。
The striped electrical connection line 2 is made of a conductive material such as metal. A specific example of metal is copper (Cu
) and aminium (AQ).

このストライプ状の電気的接続線2は折曲げが可能であ
る程度の機械的強度をもっていることが必要である。
This striped electrical connection line 2 needs to have a certain degree of mechanical strength so that it can be bent.

すなわち、上記のように半導体チップ(ペレッ1−) 
]のポンディングパッド3にその片側が取付けられたこ
の接続線2は、第2図に示すように、半導体チップ1の
側面に沿ってかつ半導体チップlの側面から離隔して折
曲げられる。この折曲げは、第2図に示すように、断面
コ字状(逆コ字状も含む)に折曲げられ、折[1,10
ずられた接続線2の他端部が半導体チップ1の裏面に位
置するように行われる。
That is, as mentioned above, the semiconductor chip (pellet 1-)
This connecting wire 2, one side of which is attached to the bonding pad 3 of ], is bent along the side surface of the semiconductor chip 1 and away from the side surface of the semiconductor chip 1, as shown in FIG. As shown in FIG.
This is done so that the other end of the shifted connection line 2 is located on the back surface of the semiconductor chip 1.

接続線2の上記他端部は実装基板4上に複数配列パター
ニングされた導体部5に接続材6により接続される。
The other end of the connection line 2 is connected to a plurality of conductor parts 5 patterned on the mounting board 4 by a connection material 6.

この実装基板4は放熱性の良い材料により構成されてい
ることがよく、例えばセラミック基板や、シリコンカー
バイド基板により構成される。半導体チップ1がシリコ
ン基板により構成されているときは、この基板1と実装
基板間の接続部の熱膨張係数差は、接続線2の弾性で吸
収されこれにより接続部の熱膨張係数差に基づく熱ひず
みの問題を解消できる。
The mounting board 4 is preferably made of a material with good heat dissipation properties, such as a ceramic substrate or a silicon carbide substrate. When the semiconductor chip 1 is made of a silicon substrate, the difference in thermal expansion coefficient at the connection between the substrate 1 and the mounting board is absorbed by the elasticity of the connection wire 2, and the difference is based on the difference in the thermal expansion coefficient at the connection. It can solve the problem of thermal distortion.

この実装基板4は、第2図では図示していないが多数の
セラミック配線基板を積層して成る多層配線基板である
ことが、高密度実装という観点から好ましい。
Although not shown in FIG. 2, the mounting board 4 is preferably a multilayer wiring board formed by laminating a large number of ceramic wiring boards from the viewpoint of high-density mounting.

実装基板4はその表面に導体パターン5が形成されてい
るが、このバターニングは周知のプリント配線技術など
により行われ、導体パターン5は例えばタングステンや
AQメタライズ層により構成されている。
A conductor pattern 5 is formed on the surface of the mounting board 4, and this patterning is performed by a well-known printed wiring technique, and the conductor pattern 5 is made of, for example, tungsten or an AQ metallized layer.

接続材6には例えば半田が使用される。接続材6に半田
を使用し、一方、接続線2のポンディングパッド3をC
CB方式に使用されるような半田バンブを使用する場合
には、両者の融点に差異があるものを使用し、半田接続
材6の溶融に従い半田バンプ3も共に溶融しないように
しておくことがよい。
For example, solder is used as the connecting material 6. Use solder as the connecting material 6, and on the other hand, connect the bonding pad 3 of the connecting wire 2 with C.
When using solder bumps such as those used in the CB method, it is preferable to use solder bumps that have different melting points, so that the solder bumps 3 do not melt together with the melting of the solder connection material 6. .

上記のように、本発明においては、接続線2により半導
体チップ1と実装基板4との電気的接続を行うと共に、
半導体チップ1の裏面を第2図に示すように実装基板4
にボンディングする。このボンディングはフェイスアッ
プボンディングにより行われる。
As described above, in the present invention, the semiconductor chip 1 and the mounting board 4 are electrically connected by the connection wire 2, and
The back side of the semiconductor chip 1 is mounted on a mounting board 4 as shown in FIG.
Bond to. This bonding is performed by face-up bonding.

半導体チップ1の裏面にメタライズ層 を前記導体パタ
ーン5と同様に形成しておき、接続部材8を介して半導
体チップ1を実装基板4の導体部5にボンディング(ペ
レット付け)する。
A metallized layer is formed on the back surface of the semiconductor chip 1 in the same manner as the conductor pattern 5, and the semiconductor chip 1 is bonded (pellet-attached) to the conductor portion 5 of the mounting board 4 via the connecting member 8.

本発明においては、電気的接続線2による半導体チップ
1と実装基板4との電気的接続と半導体チップ1の実装
基板4へのボンディングを同時に行うことができること
を特長とする。
The present invention is characterized in that the electrical connection between the semiconductor chip 1 and the mounting board 4 via the electrical connection line 2 and the bonding of the semiconductor chip 1 to the mounting board 4 can be performed simultaneously.

すなわち、例えば、電気的接続線2の他端部具面に例え
ば、半田や銀ペーストを盛っておき、一方、実装基板4
のメタライズ層5−ににも半田や銀ペーストを盛ってお
き、これら半田や銀ペースとを熱溶融させて、上記ペレ
ット付けと電気的接続とを同時に行うことができる。
That is, for example, solder or silver paste is applied to the surface of the other end of the electrical connection line 2, and on the other hand, the mounting board 4 is
Solder or silver paste is also applied to the metallized layer 5-, and the solder or silver paste is thermally melted to effect the above-mentioned pellet attachment and electrical connection at the same time.

本発明半導体装置は、実装基板下部から外部ピンを突出
させ、キャップを気密封止するなどにより完成される。
The semiconductor device of the present invention is completed by protruding external pins from the lower part of the mounting board and hermetically sealing the cap.

〔効果〕〔effect〕

(1)電気的接続線2がコ字状に折曲げら九かつ当該接
続線の他端を半導体チップ裏面にまで這わしているので
、実装基板上に半導体チップを多数搭載することができ
、マルチチップ化による高密度実装が可能である。一般
のワイヤボンディングによればrlJ広のボンディング
エリアを必要とし、その分生導体チップをマルチにマウ
ントすることを妨げているが、本発明では複数ペレッj
・を最小面積でマウントすることができ、高密度実装に
極めて有効である。
(1) Since the electrical connection wire 2 is bent into a U-shape and the other end of the connection wire extends to the back surface of the semiconductor chip, a large number of semiconductor chips can be mounted on the mounting board. High-density packaging is possible by multi-chip. Conventional wire bonding requires a wide bonding area, which prevents the mounting of multiple conductor chips, but the present invention allows multiple pellets to be mounted.
・Can be mounted in a minimum area, making it extremely effective for high-density mounting.

(2)半導体チップと実装基板間との電気的接続及び半
導体チップのペレット付けとを同時に行うことができる
。したがって、半導体チップと′眠気的−接続線とを同
時に実装基板へ接続でき、したがって、半導体装置が比
較的簡単に迅速に製造できる。
(2) Electrical connection between the semiconductor chip and the mounting board and pellet attachment of the semiconductor chip can be performed simultaneously. Therefore, the semiconductor chip and the connection line can be connected to the mounting board at the same time, and the semiconductor device can therefore be manufactured relatively easily and quickly.

本発明は上記したマルチチップ化に際しても有用な技術
となる。
The present invention is also a useful technique when implementing the above-mentioned multi-chip system.

また、ワイヤボンディングに比して、作業能率の向りや
半導体装置の接続部信頼性も向−ヒすることができる。
Furthermore, compared to wire bonding, it is possible to improve work efficiency and reliability of the connection portion of a semiconductor device.

(3)半導体チップから発する熱は電気的接続線及びチ
ップ接続部材を通して実装基板へ逃がすことができる。
(3) Heat generated from the semiconductor chip can be released to the mounting board through the electrical connection lines and the chip connection member.

半導体チップが大消費電力のLSIであっても、半導体
チップから当該接続線を介して実装基板へ放熱でき、良
好な放熱性を確保できる。
Even if the semiconductor chip is an LSI with large power consumption, heat can be radiated from the semiconductor chip to the mounting board via the connection line, and good heat radiation performance can be ensured.

(4)半導体チップと実装基板とを接続する接続部材お
よび電気的接続線の一端部が接続する半導体チップのポ
ンディングパッド部に、半導体装置動作中に熱ひずみを
生じたとしても、当該接続線にその熱ひずみが吸収され
るため、これら接続部材やポンディングパッドに半田を
用いても十分な接続部の信頼性を確保することができる
(4) Even if thermal strain occurs in the bonding pad of the semiconductor chip to which one end of the connecting member connecting the semiconductor chip and the mounting board and one end of the electrical connection line connects, the connection line Since the thermal strain is absorbed by the bonding pad, sufficient reliability of the connection portion can be ensured even if solder is used for these connection members and bonding pads.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は」―記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。
Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the examples described above, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

例えば、前記実施例では、電気的接続線を半導体チップ
のポンディングパッドにその一端部を接続(取付)後に
当該接続線を折曲げした例を示したが、この折曲げ(曲
げ加工)は前記取付前であってもよい。
For example, in the above embodiment, an example was shown in which one end of the electrical connection wire was connected (attached) to the bonding pad of the semiconductor chip and then the connection wire was bent. It may be done before installation.

また、前記実施例では半導体チップ裏面にメタライズ層
7を設けた例を示したが、必ずしもこれを必要としない
Further, although the embodiment described above shows an example in which the metallized layer 7 is provided on the back surface of the semiconductor chip, this is not necessarily required.

さらに、前記実施例では電気的接続線の折曲げした端部
が半導体チップの裏面に位置するようにした例を示した
が、側面に沿ってかつ側面から離隔して折曲げる限り、
必ずしも半導体チップの裏面にまで当該接続線を這わせ
なくてもよい。
Furthermore, in the above embodiment, an example was shown in which the bent end of the electrical connection line was located on the back surface of the semiconductor chip, but as long as it is bent along the side surface and away from the side surface,
The connection line does not necessarily need to extend all the way to the back surface of the semiconductor chip.

さらに、前記実施例では半導体チップを実装基板平面に
実装した例を示したが、実装基板表面に溝部を設け、該
溝部内に半導体チップをマウントしてもよく、実装基板
と電気的接続線との接続位置を様々に変えることができ
る。
Further, in the above embodiment, an example was shown in which the semiconductor chip was mounted on the plane of the mounting board, but it is also possible to provide a groove on the surface of the mounting board and mount the semiconductor chip within the groove. The connection position can be changed in various ways.

さらに前記実施例では半導体チップのポンディングパッ
ドと電気的接続線の一端部とを接続する例を示したが、
半導体チップ側面に孔を穿設し、該孔内に電気的接続線
を挿入し、半導体チップ内の内部配線と結線してもよい
Furthermore, in the above embodiment, an example was shown in which the bonding pad of the semiconductor chip and one end of the electrical connection line were connected.
A hole may be formed in the side surface of the semiconductor chip, and an electrical connection wire may be inserted into the hole and connected to internal wiring within the semiconductor chip.

〔利用分野〕[Application field]

以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である半導体装置の半導体
チップの実装基板への実装技術に適用した場合について
説明したが、それに限定されるものではない。
The above explanation has mainly been about the case where the invention made by the present inventor is applied to the field of application which is the background of the invention, which is the technology for mounting a semiconductor chip on a mounting board of a semiconductor device, but the present invention is not limited thereto. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の実施例を示す要部平面図、第2図は
、第1図1−1線に沿う断面図である。 ■・・半導体チップ、2・・・電気的接続線、3・・ボ
ンディングパット、4・・・実装基板、5・・・導体部
、6・・・接続材、7・・・メタライズ層、8・・接続
部材。
FIG. 1 is a plan view of essential parts showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along line 1-1 in FIG. ■... Semiconductor chip, 2... Electrical connection line, 3... Bonding pad, 4... Mounting board, 5... Conductor part, 6... Connecting material, 7... Metallized layer, 8 ...Connection member.

Claims (1)

【特許請求の範囲】 1、半導体チップにストライプ状の電気的接続線の一端
部を接続し、当該接続線を前記半導体チップの側面に沿
ってかつ当該側面から離隔して折曲げし、折曲げした接
続線の他端部を実装基板の導体部に接続するとともに、
前記半導体チップの裏面を接続部材を介して前記実装基
板にボンディングして成ることを特徴とする半導体チッ
プの実装基板へのボンディング及び半導体チップと実装
基板間の電気的接続とを共に行った半導体装置。 2、該接続線の折曲げした端部が半導体チップの裏面に
位置するようにコ字状に折曲げして成る、特許請求の範
囲第1項記載の半導体装置。
[Claims] 1. Connecting one end of a striped electrical connection line to a semiconductor chip, bending the connection line along and away from the side surface of the semiconductor chip; Connect the other end of the connected wire to the conductor part of the mounting board, and
A semiconductor device characterized in that the back surface of the semiconductor chip is bonded to the mounting board via a connecting member, and the semiconductor chip is bonded to the mounting board and the semiconductor chip and the mounting board are electrically connected together. . 2. The semiconductor device according to claim 1, wherein the connecting wire is bent in a U-shape so that the bent end thereof is located on the back surface of the semiconductor chip.
JP8942384A 1984-05-07 1984-05-07 Semiconductor device Pending JPS60234334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8942384A JPS60234334A (en) 1984-05-07 1984-05-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8942384A JPS60234334A (en) 1984-05-07 1984-05-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60234334A true JPS60234334A (en) 1985-11-21

Family

ID=13970245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8942384A Pending JPS60234334A (en) 1984-05-07 1984-05-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60234334A (en)

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