JPS60234291A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain the high-speed working of a semiconductor memory device with low power consumption by constituting an address buffer and a pre-address decoder of the ECL (emitter coupled logic) circuit structure. CONSTITUTION:The address signal bit AO of a CMOS level is converted into an ECL level through a transistor TR10 of an address buffer constituting an ECL circuit, a level shift diode D10 and an emitter follower forming an MOSFET30 constituting a constant current source. This conversion output is supplied to the base of a differential TR11 of an address buffer which constitutes the ECL circuit with the emitter connected to a constant current source TR31 in common to the emitter of a differential TR12 together with said TR12 to which the reference voltage is applied through the base as the threshold voltage. A pre-address decoder part also applies the constitution of an ECL circuit, and an ECL circuit is used also to other address signal bits. Therefore a static RAM semiconductor device using an MOSFET to a memory array can works at a high speed with low power consumption.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is effective for use in a semiconductor memory device that constitutes a static RAM whose memory array is constituted by MOSFETs.

[Background technology]

RAM composed of bipolar transistors (
random access memory) (for example, product name HM2
Although the transistor No. 105) operates at high speed, it has the drawback of increasing power consumption because an operating current continues to flow through each transistor at all times.

1. On the other hand, a static type RAM configured with CMO3 circuits (see, for example, Magazine Electronic Materials, April 1983 issue, pages 56 to 61) has low power consumption, but on the other hand, an ECL configured with the above-mentioned bipolar type transistors.
(Emitter-coupled logic) type RAM has the disadvantage of slow access time.

Therefore, the inventor of the present invention proposed the above-mentioned CMOS static type R.
We considered achieving high-speed operation and low power consumption by using an ECL circuit that can operate at high speed in the address buffer and pre-address decoder section of AM.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device that realizes high-speed operation and low power consumption.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Invention (already required)]

Among the inventions disclosed in this application, R, representative m
A brief explanation of the main points is as follows.

That is, the address buffer and pre-address decoder of the MOS static RAM are configured by ECL circuits, and high-speed operation by the ECL circuit and low power consumption by the 0M03 circuit are realized.

〔Example〕

FIG. 1 shows the present invention as a CMOS static RAM.
A circuit diagram of an embodiment that is applicable to the following is shown. Although not particularly limited, the RAM in the figure may be a known bipolar (Bi) or 0MO5 (complementary MO3) integrated circuit (IC).
) technology on a semiconductor substrate such as a silicon single crystal. Terminals Ax, Ay, Din, Dout
, WE and C8 are its external terminals. Note that the power supply terminal is omitted in the figure. Although not particularly limited, the CMOS static type RAM of this embodiment
is designed to have a storage capacity of approximately 64 bits. In order to reduce stray capacitance in common data lines, which will be described later, the memory array is divided into 41 circuits.

One specific circuit of the memory cell MC is shown as a representative, which is a memory (drive) MO5FETQI, C2 whose gate and drain are cross-connected (latch type).
And the above MO5FETQI.

Although not particularly limited, high resistances R1 and R2 formed of a polysilicon layer for information retention are provided between the drain of C2 and the power supply voltage VDD. Transmission gates MO3FETs Q3 and C4 are provided between the common connection point of the MO3FETs QI and Q2 and the complementary data lines (or digit lines) Do and DO. Other memory cells MC also have similar circuit configurations.

These memory cells MC are arranged in a matrix, and a memory array M-ARYO is shown as a representative.
Configure. That is, the transmission gate type MO3FETQ3 . of the memory cells arranged in the same row. Gates such as Q4 are
Input/output terminals of memory cells arranged in the same column and commonly connected to corresponding word lines W1 and W2 are connected to a pair of corresponding complementary data lines DO, Do and DI, respectively.
.

Connected to Dl.

In the above memory cell MC, in order to reduce power consumption, the resistor R1 is set to a level that allows the gate voltage of MO3FETQ2 to be maintained above the threshold voltage when H05FETQ1 is turned off. It is made to have a high resistance value. Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistor R1 has enough current supply capability to prevent the information charges stored in the gate capacitance (not shown) of the MO3FET Q2 from being discharged due to the drain leakage current of the MO3FET QI.

According to this embodiment, although the memory array is manufactured by CMO5-IC technology, the memory cells MC are composed of n-channel MO3FETs and polysilicon resistance elements as described above. Compared to the case where a p-channel MO3FET is used in place of the polysilicon resistance element, the size of the memory cell and memory array can be made smaller. That is, when using a polysilicon resistor, the drive M
It can be formed integrally with the gate electrode of O3FETQI or C2, and its size can be reduced. And, like when using p-channel MO5FET,
Since it is not necessary to separate it from the driving MO3FETs QI and Q2 by a relatively large distance, no wasted blank space is created.

In the figure, the word line W1 is connected to the X address decoder
- Drive circuit DVI that receives the selection signal formed by DCR
selected by The same applies to the other word IjlW2.

The X-address decoder X-DCR is composed of mutually similar NOR gate circuits G1, 02, etc. The inputs of these NOR gate circuits Gl, 02, etc. receive an external address signal A supplied from an appropriate circuit device (not shown).
An internal complementary address signal processed by the X address buffer X-ADB receiving x is applied according to a predetermined combination.

The pair of data lines DO, Do and DI, DI in the memory array M-ARYO are each connected to a transmission gate 1-M05FET for data line selection, although it is not particularly limited.
Q9. The common data line, CDO, CD is connected via a column switch circuit composed of QlO, Qll, and G12.
Connected to O. The input terminal of the read L7 circuit R and the output terminal of the write circuit W are connected to the common data lines CDO, CDO. Other memory array M- not shown
The common data lines of ARYO to memory array M-ARY3 are also connected to corresponding input terminals of the readout circuit R, respectively.
It is connected to the corresponding output terminal of the write circuit W. The output terminal of the read circuit R sends a read signal to the data output terminal Dout, and the input terminal of the write circuit W sends a read signal to the data output terminal Dout.
A write data signal supplied from the data input terminal Din is applied.

MO5FETQ9 that constitutes the above column switch circuit.
Selection signals Yl and Y2 are supplied from the Y address decoder Y-DCR to the gates of QIO, Qll, and G12, respectively. This Y-address decoder Y-DCR is composed of mutually similar NOR gate circuits G3, G04, etc. These NOR gate circuits G3. A predetermined combination of internal complementary address signals processed by a Y address buffer Y-ADB receiving an external address signal Ay supplied from an appropriate circuit device (not shown) is applied to the input of G4.

The control circuit CON receives control signals from external terminals WE and C3 and forms an internal control timing signal.

In this embodiment, although not particularly limited, when the chip is not selected, the load MO3FETQ5 etc. of the data line and the transmission gate MO3FETQ3 etc. of the memory cell MC connected to the word line of which one is in the selected state are in the on state. In order to prevent direct current from flowing through the memory MO3FET Q1, etc., the internal chip selection signal in a non-selected state is generated by the control circuit COH at the input of the NOR gate circuit Gl, 02, etc. that constitute the X address decoder X-DCR. The high level of a makes all word lines non-selected.

FIG. 2 shows a circuit diagram of one embodiment of the readout circuit.

In this embodiment, differential bipolar transistors TI and T2 are used as the sense amplifier SAO that amplifies the read signal from the memory array M-ARYO, although not particularly limited thereto.

That is, the read voltage of the memory cell appearing in the common data CDO and CDO is the same as that of the differential transistor T.
1. Supplied to the base of T2. The common emitters of these differential transistors TI and T2 include an n-channel MO3FETQI3 which receives an operation timing signal φpao.
is provided. A similar differential transistor T3 is also applied to the memory array M-ARY3 shown as another representative.
．． A sense amplifier SA3 is provided, which includes a transistor T4 and an N-channel MO3FET QI4. The differential transistors TI, T2 and T3. Corresponding collectors such as T4 are shared and connected to a pair of input terminals of a main amplifier MA, which will be described later.

MO5 provided at the common emitter of each differential transistor
FETQI 3. The operation timing signals φpaO and φpa3 supplied to the gate of Ql4 go to a low level (
a read control signal C5+WE which becomes logic "0");
A NOR (N) receives complementary address signals axi and ayi used in the selection operation of the memory arrays M-ARYO to M-ARY3.

R) Gate circuit G5. Formed by G6. As a result, only the MOSFET that forms the operating current of one sense amplifier SA corresponding to the memory array selected for the read operation is turned on, and the MOSFETs of the remaining three sense amplifiers SA are turned off.

The collectors of the differential transistors Tl, T2 to T3, T4, which constitute each of the common sense amplifiers 5AO-3A3, are connected to the grounded amplification transistors T5, T2, T2, T3, T4, and T4, which constitute the first stage circuit of the main amplifier MA, respectively. Each is connected to the emitter of T6. These transistors T5.
76 is supplied with a bias voltage formed by the following bias circuit. In other words, between the power supply voltage ■DD and the ground potential point of the circuit,
Diode DI in series form to level shift DD.

n-channel MO3FETQ that flows bias current with D2
16 are connected in series. In addition, the diode Di is connected to an n-channel MO3FET Q23 in parallel.
The gate of each MO3FET Q23 is supplied with read control signals -p, +cs which become low level during a read operation, although this is not particularly limited. Also, the transistor T5. Each emitter of T6 has an n-channel MO3F forming its bias current.
ETQ15. Ql7 is established. These MO3FE
TQI 5. The gate of Ql 7 is supplied with a control signal C5 which becomes high level during the read operation, so that the MO3FET is activated only during the read operation.
Q15 to Q17 are turned on and form their respective bias currents.

Further, the transistor T5. Between the collector of 'T'6 and the power supply voltage VDD, there are p-channel MOS FETQ20.C connected in parallel as load means.
21 and N-channel MO3FETs Q22 and C24 are installed. The above p-channel MO3FETQ20. C2
The gate of No. 1 is always on by being constantly supplied with the ground potential of the circuit, and the gate of n-channel MO3F
The gate of ETQ22°C24 has 1. The read control signal -E1CS is supplied.

These transistors T5. The collector output of T6 is connected to the emitter follower transistor T7. The data is transmitted to the data output buffer DOB through T8.

Said transistor T7. The emitter of T8 is provided with n-channel MOS FE'r1 C18 and C19 that form its operating current, and is supplied with the readout control signal -E-C5.

In a read operation, the write enable signal WE is set to high level, and the chip selection signal Sieve is set to low level. As a result, the read control signal iE -C5 becomes high level and its inverted signal -B+C5 becomes low level.

Therefore, for example, if the address signals axi and ayl supplied at this time are at low level, NOR gate circuit G5 is opened and its output signal φpaO is at high level, MO5
FETQ13 is turned on. As a result, an operating current flows through the differential transistors Tl and T2, so that the read signal from the memory array M-ARYO is amplified and sent from the collector.

On the other hand, since the control signal WE-C5 of the main amplifier MA becomes high level, the MO3FETQ1 constituting the current source
5 to Q19 are turned on to form operating currents in the respective transistors T5 to T8, so the output signal of the sense amplifier SAO is amplified and the data output cover sofa D
2 is supplied to OB (not shown), so the read output signal Dout from the external terminal
is obtained.

Note that the sense amplifiers SA1 to SA3 of the other memory arrays M-ARYI to M-ARY3 have output high impedance because their operation timing signals pal to φpa3 become low level and MO8FETQ14 etc. that form the operating current are turned off. state. As a result, the main amplifier MA has the memory array M-AR selected above.
Only the output current of YO is supplied.

In addition, in the write operation, the write enable signal W
Since E becomes low level, the above control signal WE -C5
becomes low level, and WE+'C5 becomes high level. As a result, the MO which forms the operating current of the sense amplifiers SAO to S A 3 and the amplification transistor of the main amplifier MA
All 3FETQI 3 to Q19 are turned off and their operations are prohibited. At this time, the bias voltage of the first stage circuit of the main amplifier MA is MO3FETQ
The on-state voltage of 23 is approximately VDD-Vf (Vf is the forward voltage of diode D2). Further, the N-channel MO5FETs Q22 and Q24 serving as load means are also turned on, and the emitter follower transistors T7. T
By raising the base potentials of both 8 and 8, the P-channel inter-channel O3FETs forming the input stage circuit of the data output cover sofa circuit DOB that receives the output signal are both turned off (not shown).

Note that when forming the operating current of the bipolar transistor, the MOSFET is operated in the saturation region. As a result, the MOS FET can generate a constant (constant current) operating current with respect to the bipolar transistor.

FIG. 3 shows a circuit diagram of an embodiment of the address buffer X-ADB (Y-ADB) and address decoder X-DCR (Y-DCR) in the embodiment circuit of FIG. 1.

Although not particularly limited, 8-bit address signals AO to A
7, 256 word lines (or complementary data lines)
When forming the selection signal of 8-bit address signal A
O-A7 is AO~A2°A3~A5 and A6. It is divided into three parts like A7.

Of these, two address buffer circuits receiving the address signals AO-A2 are shown as representatives in the figure. That is, the address signal AO supplied from the external terminal is transmitted through a transistor TIO, a level shift diode DIO, and an MO constituting a constant current source for converting the CMOS level address signal AO into an ECL level signal.
It is supplied to an emitter follower circuit consisting of 3FETQ30. This level conversion output is the differential transistor T11
supplied to the base of A reference voltage VBB as a logic threshold voltage is supplied to the base of a differential transistor T12 paired with the differential transistor Tll. And the differential transistors Tll, T1
The common emitter of 2 is a MO3FET as a constant current source.
Q31 is provided. Further, the differential transistor Tl
Load resistors R1 and R are installed on the collectors of R1 and T12, respectively.
5 2 will be provided. The differential transistor Tll.

The collector output of T12 is output from a multi-emitter output transistor T13. It is output through T14. The address buffer circuit shown as another representative which receives the address signal A2 is also constituted by a circuit similar to the above.

The pre-address decoder uses the above 3-bit address signal AO-A2 to output 1/8 of 0 to 7 decoded output O to
7. That is, each of the four internal complementary address signals aO to a2 . It is constructed with a wired logic configuration in which multi-emitters that respectively transmit aO to a2 are connected in a predetermined combination.

For example, decode output 0 is aQ, al, a2.1 is aQ
.

al, a2.2 is aQ, al, a2-...7 is aO,
It is constructed by connecting emitters that send out al and a2, respectively.

The address buffer and pre-address decoder receiving other address signals A3 to A5 and the address buffer and pre-6 address decoder receiving address signal A6.7 are also constructed of similar circuits as described above.

The output signal of the above pre-address decoder is output from P-channel MO3FETQ35 and N-channel MO3FETQ36.
And it is supplied to a CMOS inverter circuit constituted by a level shift diode Dll provided between the source of the MO3FET Q36 and the ground potential point of the circuit.

The reason why the level shift diode Dll is provided is to level shift the logic threshold voltage of the CMOS inverter circuit to match the level with the output signal of the pre-address decoder formed by the ECL circuit. In other words, since the ECL low level is at an intermediate level higher than the ground potential, the N-channel MO3FET Q36 is turned off even at this low level.

The output signal of the CMOS inverter circuit is made to a complete CMOS level by the CMOS inverter circuit IVI, is configured by a CMOS NOR gate circuit G7, and is supplied to an address decoder circuit for selecting a word line (or complementary data line). This CMOS NOR gate circuit G7 receives the address signals A3 to A5 and A6. A
The output signal of a similar address buffer and pre-address decoder receiving 7 is provided.

The above three sets of pre-address decoder outputs are each 1/
8. Since 1/8 and 1/4 selection signals are formed, a total of 1/256 word line or complementary data line selection signals can be formed.

In this embodiment, MO5 constituting the constant current source is
A chip selection signal CS is supplied to the gates of FETQ30 to Q34, and these MO3
FETs Q30-Q34 are made to operate in the saturation region. This prevents wasteful current consumption in the chip non-selected state in the ECL circuit constituting the address buffer and pre-address decoder.

[Effects] (1) By configuring the address buffer and the pre-address decoder that receives the output from the ECL circuit, it is possible to achieve the effect that high-speed operation can be achieved. By the way, if the address buffer and address decoder are all constructed with 0M03 circuits, it will take about 14r+s from the time the address signal is supplied until the word line or complementary data line selection signal is formed, but the above ECL By using a circuit, it is possible to achieve a speed increase of about 8 na.

(2) Since the memory array and the circuit for forming the selection signal are constituted by 0M03 circuits, it is possible to significantly reduce power consumption compared to bipolar RAM.

(3) By incorporating the address buffer, pre-address decoder, sense amplifier, and main amplifier into ECL circuits, it is possible to realize higher-speed operation.

(4) As a constant current source that forms the operating current of the ECL circuit, a MOS FET that is turned on only during its operation period and passes a constant current of 9 Ω is used.
This has the effect of reducing the power consumption of the L circuit.

(By using a differential transistor composed of bipolar transistors as the sense amplifier in the 51CM OS static RAM, only a small current inversely proportional to the current amplification factor flows through the data line. In other words, the memory cell Even if the cell size of the sense amplifier is reduced to reduce its current drive capability, the operating current of the sense amplifier can be increased.This has the effect of increasing storage capacity and achieving high-speed read operations.

The invention made by the present inventor has been specifically explained above based on Examples, but it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the memory cell of the embodiment circuit of FIG. 1, p
An inter-channel O3FET may also be used.

Also, instead of the above 0M03 circuit, an n-channel MO3F
0 ET or a p-channel MO8FET. Further, the specific circuit configuration and timing control of the peripheral circuit can take various embodiments.

[Application field]

The present invention can be widely used as a semiconductor memory device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention applied to a CMOS static RAM, and FIG.
FIG. 3 is a circuit diagram showing an example of the readout circuit in the embodiment shown in FIG. 1. FIG. 3 is a circuit diagram showing an example of the address buffer and address decoder in the embodiment shown in FIG. X-ADB...X address buffer, Y-ADB...Y
Address buffer, X-DCR...X address decoder, Y-DCR...Y address decoder□, MC...memory cell, W...write circuit, R...read circuit, SA
O~SA3...Sense amplifier, MA...Main amplifier,
DOB...Data output buffer, DIB...Data buffer sofa, CON...Control circuit 3 Figure 2 "'""''' Figure 3 A Cold reading, -μΔs

Claims (1)

[Claims] 1. An address buffer circuit constituted by an ECL circuit, a pre-address decoder circuit that receives its output signal, and a CMOS address decoder that receives the pre-address decoder circuit and forms a memory array selection signal. What is claimed is: 1. A semiconductor memory device comprising: a data circuit; 2. The semiconductor memory device according to claim 1, wherein the memory array constitutes a static type RAM constituted by MOSFETs.