JPH0279292A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To contrive low energy consumption and a high speed by providing a capacitor having specific electrostatic capacity between the input node of a voltage generating circuit and the ground potential of the circuit, and temporarily increasing an input voltage at the beginning of the operating condition of a voltage generating circuit. CONSTITUTION:In a Bi.CMOS dynamic type RAM, etc., to provide a voltage generating circuit VG and to adopt a power source switching system, a capacitor C1 having the specific electrostatic capacity between the input node of a voltage generating circuit VG and the ground potential of the circuit is provided, and at the beginning of the operating condition of the voltage generating circuit VG, the absolute value of the input voltage is temporarily increased. Thus, since the rising of the output voltage of the voltage generating circuit VG can be made faster, as a result, the operation of the input circuit of an address buffer, etc., can be made faster, and by adopting the power source switching system, the access time of the Bi.CMOS dynamic type RAM, etc., can be made faster while the low energy consumption is being promoted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, such as a 91-CMOS dynamic RAM (Rand
The present invention relates to a technique that is particularly effective when used in applications such as access memory.

[Conventional technology]

There is a dynamic RAM whose basic configuration is a memory array in which dynamic memory cells are arranged in a grid.

Regarding dynamic RAM, for example, Japanese Patent Application Laid-Open No. 60
-185291, etc.

[Problem to be solved by the invention]

Prior to the present invention, the inventors of the present invention had developed a so-called B-type RAM in which the peripheral circuit of the dynamic RAM was constructed of bipolar transistors and CMOS (complementary MO5).
Developed i-CMOS dynamic RAM. Also,
In order to further reduce the power consumption of j-CMOS dynamic RAM, a voltage generation circuit for supplying a predetermined base voltage to a bipolar transistor that constitutes a constant current source in an address input circuit, etc. CM
We have developed a so-called power switch method that selectively puts the OS dynamic RAM into the active state when it is in the selected state.

Figure 5 shows a B1/CMO that uses the above power switch method.
SMOS DYNAMITSU AM row address buffer RAB
A partial circuit diagram is shown.

In Fig. 5, Bi CMOS dynamic RAM
The row address buffer RAB includes a plurality of unit address buffers UABO, etc. provided in response to multiple hits of the X address signal AXO, etc. These unit address buffers are bipolar transistors (hereinafter simply referred to as transistors). Input circuit IC whose basic configuration is T2
The current switch circuit C8 includes a current switch circuit C8 having a basic configuration of differential transistors T3 and T4.
Furthermore, a predetermined base voltage vb is supplied from the voltage generation circuit VG to these constant current sources including a plurality of constant current sources made up of transistors T7 to T9 and resistors R4 to R6.

The voltage generating circuit vG includes a transistor T1 provided between its output node and the ground potential of the circuit.
2 are provided in parallel configuration. Furthermore, resistors R2 and R3 are provided between the base of the transistor T1 and the output node and the ground potential of the circuit, respectively. The output node of the voltage generation circuit VG is further connected to an N-channel MO3FET.
It is coupled to the circuit power supply voltage via QII and resistor R1. The internal control signal ae is supplied to the gate of the MO3FETQI 1, and the inverted signal of the internal control signal ae by the inverter circuit N1 is supplied to the gate of the MOSFETQ12. Here, the internal control signal ae is
When the B i -CMOS dynamic RAM is brought into a selected state, it is selectively set to a high level.

When the Bi-CMOS dynamic RAM is in the selected state and the internal control signal as is set to high level, the MO
3FET QI 1 is turned on. For this reason, the voltage generating circuit VG is in an operating state, and for example, the voltage is 1.5 Vat.
(Here t', vBE indicates the base-emitter voltage of an NPN transistor.) A stable base voltage vb is formed.

As a result, the current switch circuit C8 such as the row address buffer RAB is brought into operation. On the other hand, Bi・CMO
When the S dynamic type RAM is in a non-selected state and the internal control signal ae is set to low level, MOSFET QI
1 is turned off and MO3FETQI 2 is turned off instead.
is turned on.

Therefore, the voltage generating circuit VC becomes inactive, and the base voltage vb' is fixed at the ground potential of the circuit. Therefore, in a large number of unit address input circuits provided in the row address buffer RAB, etc., the current switch circuit C8
The wasteful operating current flowing through the differential transistors T3 and T4 and the output limiter follower circuit is stopped. As a result, the power consumption of the Bi-CMOS dynamic RAM during standby can be reduced.

However, the B1, which uses the power switch method as described above,
The inventors of the present application have discovered that the CMOS dynamic RAM has the following problems. That is, as is well known, the parasitic capacitance C3 present in the collector region of the transistor Tl and the base regions of the transistors T7 to T9 is coupled to the output node n2 of the voltage generating circuit VC. Therefore, as shown in FIG. 4, the output voltage of the voltage generating circuit VC, that is, the base voltage Vb rises slowly. Therefore, the operation of the current switch circuit cs such as the row address buffer RAB is delayed, and as a result, the speeding up of the access time of the Bi-CMOS dynamic RAM is limited.

An object of the present invention is to speed up the rise of the output voltage of a voltage generating circuit that is selectively activated. Another object of the present invention is to provide a B L-CMOS dynamic RAM equipped with a voltage generation circuit and employing a power switch system.
The aim is to speed up the access time of etc.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, in Bi/CMOS dynamic RAM, etc., which is equipped with a voltage generation circuit and uses a power switch method,
A capacitor with a predetermined capacitance is provided between the input node of the voltage generation circuit and the ground potential of the circuit, and the absolute value of the input voltage is temporarily increased when the voltage generation circuit is put into operation. It is something.

[For production]

According to the above-mentioned means, the rise of the output voltage of the voltage generation circuit can be made faster, and as a result, the operation of input circuits such as address buffers can be made faster. As a result, by adopting the power switch method, it is possible to reduce the power consumption and speed up the access time of Bi/CMOS dynamic RAM and the like.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of a Bi-CMOS dynamic RAM to which the present invention is applied. Further, FIG. 1 shows a partial circuit diagram of an embodiment of the row address buffer RAB of the Bi CMOS dynamic RAM shown in FIG. 2, and FIG.
1. A signal waveform diagram of an embodiment of a CMOS dynamic RAM is shown. According to these figures, an overview of the configuration and operation of the Bi-CMOS dynamic RAM of this embodiment and its characteristics will be explained.

Note that the circuit elements in FIG. 1 and the circuit elements constituting each block in FIG. It is formed. In Figure 1, an arrow is added to the channel (back gate) section of the MOS.
The FET is a P-channel type, and the N
It is shown separately from the channel MO3FET. Furthermore, all the illustrated bipolar transistors are NPN type transistors.

The 81 CMOS dynamic type RAM of this embodiment is as follows:
By designing the arrangement of input/output terminals to be the same as that of a conventional static type RAM, the RAM has a so-called pseudo-static type RAM configuration.

Therefore, the row address signal, that is, the X address signal q
AXo to AXi and column address signals, that is, Y address signals AYO to AYj, are each input via separate external terminals. Bi/CMOS dynamic RA
M has a chip enable signal CE, as a control signal.
A write enable signal WE and an output enable signal OE are supplied, and a refresh control signal RF for controlling the refresh operation is further supplied. These address signals, control signals, and input/output data are
The signal is set to the CL level, and its signal amplitude is set to, for example, 0.8V. For this reason, Bi CMOS dynamic RAM
row address buffer RAB.

Column address buffer CAB, data input/output circuit I1
0 and timing generation circuit TG includes a level conversion circuit for converting an input signal of ECL level to MOS level and converting an output signal of MOS level to ECL level.

B i -CMOS dynamic RAM of this embodiment
, each address buffer and data input/output circuit I
As will be described later, the LO etc. include a current switch circuit consisting of a level determination circuit whose basic configuration is a pair of differential transistors, and a pair of output emitter follower circuits that transmit complementary output signals of this level determination circuit. These level determination circuits and output limiter follower circuits are each provided with a constant current source whose basic configuration is a bipolar transistor, and a voltage for supplying a predetermined base voltage to the transistors that constitute these constant current sources. A generating circuit is provided respectively. In this embodiment, the voltage generating circuit is selectively brought into operation when the Bi-CMOS dynamic RAM is brought into the selected state. In other words, the operation of the voltage generating circuit VC is stopped while the Bi-CMOS dynamic RAM is in the non-selected state. Therefore, during this time, the operating current of a relatively large number of current switch circuits provided corresponding to the address signal and the λ card data is cut off, and the operation thereof is stopped.

Therefore, in the Bi-CMOS dynamic RAM of this embodiment, power consumption during standby is significantly reduced.

In Figure 2, Bi CMOS dynamic RAM
includes, but is not particularly limited to, two memory arrays MARYO and MARYl arranged symmetrically, and a sense amplifier 5APO provided corresponding to these memory arrays.
5API, 5ANO, 5ANI and column switches C5O and C5l.

Memory arrays MARYO and MARYI have a plurality of word lines arranged in parallel in the vertical direction, a plurality of complementary data lines arranged in parallel in the horizontal direction, and a grid pattern at the intersections of these word lines and complementary data lines. and a plurality of dynamic memory cells arranged in the memory cells.

Word lines constituting memory arrays MARYO and MARYI are connected to corresponding row address decoders RADO and R.
It is coupled to A and DI and is alternatively set in a selected state.

The row address decoders RAD (l and RADl) are supplied with a predetermined predecode signal from the pre-row address decoder PRAD, although this is not particularly limited. The row address decoders RADO and RADl decode the corresponding memory according to these predecode signals. Array MARYO,,
and MARYI are alternatively set to a high level selected state.

The pre-row address decoder PRAD includes, but is not particularly limited to, complementary internal address signals axQ to axi of the row address pants 7RAB (1 via excluding the most significant bit).
-1 (here, for example, the non-inverted internal address signal axQ and the inverted internal address signal aX λ are expressed as complementary internal address signals JO; the same applies hereinafter).

Also, a timing signal φX is output from the timing generation circuit TG.
is supplied. The pre-row address decoder PRAD is
By setting the timing signal φX to high level,
Selectively activated. In this operating state, the burrow address decoder PRAD decodes the complementary internal address signals xQ to axL-1 in a predetermined combination, forms the predecode signal, and supplies it to the row address decoder RAD.

Although not particularly limited, the row address buffer RAB is supplied with l+1 bits of X address signals AXO to AXi via external terminals AXO to AXI, and is supplied with t+1 bits of refresher address signals arQ to AXi from the refresh address counter RFC. ari is supplied.

Also, a timing signal φ is output from the timing generation circuit TG.
ce and φref are supplied. Here, the timing signal φcs is selectively set to a high level at a predetermined timing when the chip enable signal CE is set to a low level and the Bi-CMOS dynamic type RAM is placed in a selected state. Further, the timing signal φref is set when the refresh control signal RF is set to low level and the Bi/CMOS dynamic type RAM is placed in the refresh mode.
Selectively set to high level.

In this embodiment, the row address buffer RAB is
In particular, 5IIrR, but not the above timing signal φ
a timing setting circuit TS receiving ce and φref;
i provided corresponding to the X address signal AXO-AXi
+1 unit address buffer.

Timing setting circuit TS of row address buffer RAB
Although not particularly limited, as shown in FIG. 1, a delay circuit DLI centered on a delay capacitor C2;
Similarly, a delay circuit D centered around a delay capacitor C3
The timing signal φce supplied from the timing generation circuit TG, including L2, is delayed by the delay circuit DLI and then output as the internal signal dce to the NOR gate circuit N0.
G1 and one input terminal of NOC,2.

The other input terminal of the NOR gate circuit N0G2 has a tar
A timing signal φr'ef is supplied from the timing generation circuit TG, and an inverted signal of the timing signal φraf is supplied to the other input terminal of the NOR gate circuit N0G1. The internal signal dce is further delayed by the delay circuit DL2 and then supplied to one input terminal of the NOR gate circuit N0G3 as the internal signal d2. The other input terminal of the NOR gate circuit N0G3 is supplied with an inverted signal of the timing signal φCe.

From these facts, the output signal of the NOR gate circuit N0G1, that is, the inverted internal control signal rg, is set to the internal signal dce after the Bi/CMOS dynamic RAM is selected in the refresh mode and the timing signal φref is set to high level. Until it is set to high level, it is set to high level. In addition, the output signal of the NOR gate circuit N0G2, that is, the inverted internal control signal
The dynamic RAM is set to a selected state in the normal operation mode and the timing signal φref is set to a low level until the internal signal dce is set to a high level. Furthermore, the output signal of the NOR gate circuit N0G3, that is, the internal control signal as, is a Bi.CMOS
After the dynamic RAM is selected and the timing signal φce is set to a high level until the internal signal d2 is set to a high level, the internal signal d2 is temporarily set to a high level. These inverted internal control signals rg and xg and internal control signal ae are commonly supplied as gate control signals to each unit address buffer, as will be described later.

Each unit address buffer of the row address buffer RAB, as represented by the unit address buffer UABO in FIG. and a current switch circuit C8, and
Two sets of gate circuits G configured as clocked inverters
XP.

The transistor T7 includes GXN, GRP, GRN, latches LP, LN, and address drivers ADP, ADN, respectively, and also constitutes a unit address buffer of the row address buffer RAB of this embodiment and a constant current source of the current switch circuit C8. -T9 (second bailer transistor) each includes a voltage generating circuit VG that supplies a predetermined base voltage vb.

Hereinafter, the unit address buffer of the row address buffer RAB of the dynamic RAM will be explained using the unit address buffer UABO as an example.

In Fig. 1, E input via external terminal AXO
CL level X address signal A X Oi! , is supplied to the base of the transistor T2 constituting the input circuit IC. Two constant current sources having different conductances and selectively enabled according to the internal control signal as are provided in parallel between the emitter of the transistor T2 and the ground potential of the circuit. When the BL-CMOS dynamic RAM is in a non-selected state and the internal control signal ae is set to a low level, the emitter load of the transistor T2 is increased. Further, when the Bi-CMOS dynamic RAM is selected and the internal control signal as is temporarily set at high level, the emitter load of the transistor T2 is reduced. As a result, the power consumption of the input circuit IC when the Bi-CMOS dynamic RAM is not selected is reduced, and the power consumption of the input circuit IC when the Bi-CMOS dynamic RAM is selected is reduced.
The operation of C is sped up.

The output signal of the input circuit IC, that is, the emitter voltage of the transistor T2, is supplied to the base of the transistor T3 that constitutes the current switch circuit cs.

A predetermined reference potential Vr is supplied to the base of a transistor T4 which is differentially connected to the transistor T3. A constant current source consisting of a transistor T7 and a resistor R4 is provided between the commonly coupled emitters of the differential transistors T3 and T4 and the ground potential of the circuit. The base of the transistor 1-7 is connected to a voltage generating circuit VG, which will be described later.
A predetermined base voltage vb is supplied. This base voltage v
As will be described later, when the Bi-CMOS dynamic RAM is in a non-selected state, b is at a low level similar to the ground potential of the circuit, and when the Bi-CMOS dynamic RAM is in a selected state, the internal control signal ae is set to a low level. By temporarily setting the voltage to a high level, the voltage becomes 1.5 times the base-emitter voltage VF3E of an NPN transistor, that is, 1.5VBE. Differential transistor T3/T4
is selectively activated by temporarily setting the internal control signal ae to a high level and setting the base voltage vb to 1.5 V BE, and sets the reference potential Vr to the logic threshold level to set the X address. It functions as a level determination circuit that prunes the level of signal AXO.

Although not particularly limited, the collector potentials of the differential transistors T3 and T4 are outputted via an output follower circuit including transistors T5 and T6, and are used as an inverted internal signal xO and a non-inverted internal signal xO. transistor T
Constant current sources each consisting of a transistor T8 and a resistor R5, and a transistor T9 and a resistor R6 are provided between the emitters of the transistors T5 and T6 and the ground potential of the circuit. The base voltage vb is commonly supplied to the bases of these transistors T8 and T9. As a result, the output emitter follower circuit, which has the basic configuration of transistors T5 and T6, is selectively enabled by setting the Bi CMOS dynamic RAM to a selected state and temporarily setting the internal control signal ae to a high level. state.

In this way, in a large number of unit address buffers provided corresponding to each address signal, the constant current source that supplies operating current to the differential transistor of the current switch circuit or the output emitter follower circuit is selectively activated. As a result, the power consumption of the B i -CMOS dynamic RAM during standby is significantly reduced.

By the way, although the voltage generating circuit VG provided in each unit address buffer 1 is not particularly limited, its output node n
2 and the ground potential of the circuit.
The basic configuration is 1 (first bipolar transistor). This transistor T1 includes a clamp circuit consisting of two diodes D1 and B2, and an N-channel MOS
FETQ12 is provided in parallel configuration. Further, a resistor R2 (first resistor means) and a resistor R3 (second resistor means) are provided between the base of the transistor T1, the output node n2, and the ground potential of the circuit, respectively. Furthermore, an N-channel MO5FET QII is connected between the input node n1 of the voltage generation circuit VG and the output node n2.
(switch means) is provided. Further, a resistor R1 (third resistance means) and a capacitor C1 are provided between the human power node n1 and the power supply voltage and ground potential of the circuit, respectively. The above-mentioned internal control signal ae is supplied to the gate of MO5FETQI 1, and the MOSFETQI 1
The gate of No. 2 is supplied with an inverted signal of the internal control signal ae by the inverter circuit Nl.

When the Bi CMOS dynamic RAM is in a non-selected state and the internal @ control signal ae is set to low level, M
O3FETQI 1 is turned off and MO5FETQ
I2 is turned on. Therefore, as shown in FIG. 3, the output node n2 of the voltage generating circuit VG is fixed at a low level such as the ground potential of the circuit. At this time, since the capacitor CI is charged via the resistor R1, the input node n1 of the voltage generating circuit VG is set to a high level like the power supply voltage Vcc of the circuit.

When the Bi-CMOS dynamic RAM is selected and the internal control signal ae is temporarily set to a high level, the charge accumulated in the capacitor C1 is transferred to the capacitor C.
1 and the parasitic capacitance C3 coupled to the output node n2 of the voltage generating circuit VG. As a result, the output node n2 of the voltage generation circuit VC is
- the required predetermined level as the base voltage vb, i.e. 1.5V, after being rapidly raised to a relatively high level;
It converges to BH and is stabilized. As a result, the base voltage v
The rise time t1 of b is the same as that of the conventional B shown in FIG.
This is significantly shortened compared to the rise time t2 of the base voltage vb of the i-CMOS dynamic RAM. This speeds up the operation of the current switch circuit CS, and as a result, speeds up the access time of the Bi-CMOS dynamic RAM.

The non-inverted output signal xO of the current switch circuit CS is inverted and transmitted to the latch LP via the gate circuit GXP while the above-mentioned inverted internal control signal xg is at a high level. The latch LP is brought into a latched state when the inverted internal control signal Xg is set to a low level and the internal control signal 01 xi is set to a high level. The output signal of latch LP is further inverted by address driver ADP and supplied to pre-row address decoder PRAD as non-inverted internal address signal axQ. Similarly, the inverted output signal xO of the current switch circuit CS is the inverted internal control signal 7.
While T is set to high level, it is inverted and transmitted to latch LN via gate circuit GXN. The latch LN is brought into a latched state when the inverted internal control signal 7 is set to a low level and the internal control signal xji is set to a high level.

The output signal of latch LN is further inverted by address driver ADN and supplied to pre-row address decoder PRAD as inverted internal address signal axQ.

When the Bi-CMOS dynamic RAM is set to the refresher mode and the inverted internal control signal rg is set to high level instead of the inverted internal control signal xg, the unit address buffer UABO receives the refresh signal supplied from the refresh address counter RFC. address signal ar
Select Q.

Based on these address signals, the non-inverted internal address signal axQ and the inverted internal address signal axQ are
is formed and supplied to the pre-row address decoder PRAD.

@2 In figure 2, refresh address counter RFC
Although not particularly limited, performs a stepping operation in accordance with a timing signal φrc supplied from a timing generation circuit TO to form the refresh address signals arQ to ari.

On the other hand, complementary data lines constituting memory arrays MARYO and MARYI are coupled on one side to corresponding m-position paths of corresponding sense amplifiers 5APO and SAP1. On the other hand, it is coupled to corresponding unit circuits of corresponding sense amplifiers 5ANO and 5AN1, and further coupled to corresponding unit circuits of corresponding column switches C8O and CSI.

Sense amplifiers 5APO and 5API are connected to memory array M
It includes a plurality of unit circuits provided corresponding to each complementary data line of ARYO and MARYI.

These unit circuits include, but are not particularly limited to, circuits whose bases and drains are cross-coupled to each other and further coupled to the non-inverting signal line and the inverting signal line of the corresponding complementary data line.
The commonly coupled sources of these MOSFETs, each including a pair of P-channel MO3FETs, are commonly coupled to a common source line SP, not shown, and are further coupled to the power supply voltage of the circuit via a P-channel drive MO3FET. The gate of the drive MO3FET is supplied with an inverted signal of the timing signal φpa from the timing generation circuit TO.

Similarly, these unit circuits, including a plurality of unit circuits provided corresponding to the sense amplifiers 5ANO and 5AN11* and the memory arrays MARYO and MARYI, have their bases and drains cross-coupled to each other, although this is not particularly limited. and a pair of N-channel MO3Fs further coupled to the non-inverting signal line and the inverting signal line of the corresponding complementary data line.
The commonly coupled sources of these MOSFETs, each including ET, are commonly coupled to a common source line SN, not shown, and further coupled to the ground potential of the circuit via an N-channel drive MO3FET. Above drive MO3F
The timing signal φpa is supplied to the gate of ET.

As a result, a pair of P-channel MO3FETs provided in each unit circuit of sense amplifiers 5APO and 5AP1 and a pair of N-channel MO8FETs provided in corresponding unit circuits of sense amplifiers 5ANG and 5AN1 constitute one unit amplifier circuit. . These unit amplifier circuits are
When the timing signal φpa is set to high level and the power supply voltage and ground potential of the circuit are supplied to the common source lines SP and SN, the circuit is selectively brought into an operating state.

In this operating state, each unit amplifier circuit amplifies the minute read signal output from the plurality of memory cells coupled to the selected word line of the memory arrays MARYO and MARYI via the corresponding complementary data line, and A binary read signal of level or low level is used.

Column switches C8O and C5I include, but are not particularly limited to, a plurality of unit circuits provided corresponding to each complementary data line of memory arrays MARYO and MARYl. and write complementary common data line W100L or WIOI
A pair of switches MO3 provided between L, 100R, or WIOIR (here, for example, the non-inverted signal line W100L and the inverted signal line W100L are collectively expressed as a write complementary common data line W100L, the same applies hereinafter).
Switches M of adjacent unit circuits each including a FET
The gates of the OSFETs are commonly coupled, and a corresponding write data line selection signal is supplied from a column address decoder CAD. This allows memory array MAR
Complementary data lines of YO and MARYI are Bi/CMOS
When the dynamic RAM is set to write mode and the corresponding write data line selection signal is alternatively set to high level, two sets are simultaneously selected and the corresponding write complementary common data lines W100L and WIOIL or WlooR and WIOIR are selected. Selectively combined.

Each unit circuit of column switch C8O and CSI is further connected to the ground potential of the circuit and the read complementary common data line R100.
Two pairs of N-channel MOs provided in series between L or RIOIL or R100R or RIOIR
Of these, one pair of MOSFEs each containing 5FETs.
T has its gates connected to memory arrays MARYO and MAR
By being coupled to the non-inverted signal line and the inverted signal line of the corresponding complementary data line of YI, it functions as an amplifying MO8FET. Further, the gates of the other pair of MOSFETs are commonly coupled to the gates of a similar pair of N-channel MO3FETs in the adjacent unit circuits, and corresponding read data line selection signals are supplied from the column address decoder CAD, respectively. Thus, it functions as a switch MO3FET. As a result, two sets of complementary data lines of memory arrays MARYO and MARYl are simultaneously selected by setting the Bi CMOS dynamic RAM to the read mode and setting the corresponding read data line selection signal to a high level alternatively. and are selectively connected to the read complementary common data lines R100L and RIOIL or the line 100R and RIOIR.

That is, in the dynamic RAM of this embodiment, two sets of complementary common data lines for writing and two sets of complementary common data lines for reading are separately provided, and the memory array MARY
Two sets of O and MARYI complementary data lines are each selected and selectively connected to a complementary common data line for writing or reading. At this time, the complementary common data line for writing is directly coupled to the selected complementary data line via the corresponding switch MOSFET of column switch C5O or C3I. However, the complementary common data line for reading is connected to the column switch C8O or C81.
is indirectly coupled to the selected complementary data line through the gate of the corresponding amplifying MO3FET. This limits the signal amplitude of the complementary common data line for reading, and speeds up the reading operation of the Bi-CMOS dynamic RAM.

A predetermined predecode signal is supplied to the column address decoder CAD from the column address decoder PCAD. The column address decoder CAD selectively sets the corresponding write data line selection signal or read data line selection signal to a high level selection state according to these predecode signals.

Although not particularly limited, the column address decoder PCAD receives the most significant bit from the column address buffer CAB as a complementary internal address signal ayQ of 11<j bits.
ayj-1 is supplied, and a timing signal φy is supplied from the timing generation circuit TG. The virtual column address decoder PCAD is selectively put into an operating state when the timing signal φy is set to a high level. In this operating state, the Bricolumn address decoder PCAD
decodes the complementary internal address signals ayO to ayj-1 in a predetermined combination to form the predecoded signal and supplies it to the column address decoder CAD.

Column address buffer CAB connects external terminals AYO to A
It holds Y address signals AYO to AYj of j+1 pits supplied via Yj, and forms complementary internal address signals ayQ to ayj based on these address signals.

Of these, the complementary internal address signal ayJ of the most significant bit
are supplied to the main amplifiers MAO and MAI, and the other complementary internal address signals ayQ to ayj-1 are supplied to the virtual address decoder PCAD as described above. In this example, column address buffer C
AB is similar to the above row address buffer RAB, and Y
J provided corresponding to address signals AYO to AYj
These unit address buffers, including the unit address buffers of +lm, can be selectively brought into operation according to the internal control signal ae, that is, the timing signal φco, similar to the unit address buffers of the row address buffer RAB shown in FIG. A voltage generating circuit VG whose input voltage is temporarily increased when the voltage is initially put into an operating state.
As a result, the current switch circuit included in each unit address buffer of column address buffer CAB is
Low power consumption can be achieved without hindering high-speed operation.

Memory array MARYO by column switch C8O
One of the write complementary common data lines W100L and light 101L and the read complementary common data lines R100L and RIOIL to which the two sets of complementary data lines are selectively connected is coupled to the main amplifier MAO, and the other is coupled to the main amplifier MA1. is combined with Similarly, write complementary common data lines W100R and WIOIR and read complementary common data lines 100R% and RIOIR, to which two sets of complementary data lines of memory array MARYI are selectively connected by column switch C8l, are connected to the main amplifier. connected to MAO, and the other side is main amplifier M
Coupled to AL.

Main amplifiers MAO and MAI each include two write amplifiers and two read amplifiers, although they are not particularly limited. Of these, the output terminal of the first write amplifier provided in main amplifier MAO is connected to the write complementary common data line -
WlooL, and the output terminal of the second write amplifier is coupled to write complementary common data line W100R. Similarly, the output terminal of the first write amplifier provided in the main amplifier MAL is connected to the write complementary common data line light 1.
01L, and the output terminal of the second light amplifier is
Coupled with write complementary common data 1QWIoIR.

A write signal wm is commonly supplied to the input terminals of these write amplifiers from the data input/output circuit I10.

Further, the timing signal φwa from the timing generation circuit TG is commonly supplied to the control terminal, and complementary internal address signals axi and yj of the most significant bit are supplied from the row address buffer RAB and the column address buffer CAB.
is commonly supplied.

For these reasons, the first write amplifier of the main amplifier MAO is selectively put into the operating state when the timing signal φW3 is set to high level and the complementary internal address signals aXl and ayj are both set to logic ``0''. It is said that
In the second write amplifier of the main amplifier MAO, the timing signal φwa is set to high level, and the complementary internal address signals aXi and ayj are set to logic "1" and logic "", respectively.
Similarly, the first write amplifier of the main amplifier MAI is activated when the timing signal φwa is set to high level and the complementary internal address, address signal axi and sat yj are set to the high level. The second write amplifier of the main amplifier MAI is selectively activated when the timing signal φWa is set to logic "0" and logic "1", respectively, and the complementary internal address signal When both axl and yj are set to logic "1", the device is selectively put into operation. In this operating state, each write amplifier forms a complementary write signal according to the write signal wm, and there are corresponding write complementary common data lines W100L and WIOIL (% is Wlo
The information is transmitted to oR and WIOIR, respectively.

As a result, the memory array MARYO (G) is MARY
A write operation is performed on one of the two memory cells selected by I.

On the other hand, the input terminal of the first read amplifier provided in the main amplifier MAO is connected to the read complementary common data line R100.
The input terminal of the second read amplifier is coupled to the read complementary common data line RE00R. 'Similarly, the input terminal of the first read amplifier provided in the main amplifier MAl is connected to the read complementary common data line RIOIL.
The input terminal of the second read amplifier is coupled to the read complementary-common data line RIOIR. The output signals of these read amplifiers are alternatively transmitted to the data input/output circuit I10 via the read signal line rm.

A timing signal φra is commonly supplied from the timing generation circuit TG to the control terminal of each read amplifier, and the row address buffer RAB and column address buffer C
Complementary internal address signals axi and ayj of the most significant bit are commonly supplied from AB.

For these reasons, the first read amplifier of the main amplifier MAO is selectively put into the operating state when the timing signal φra is set to high level and the complementary internal address signals 1xl and ayj are both set to logic "0". Then, in the second read amplifier of the main amplifier MAO, the timing signal φra is set to high level, and the complementary internal address signals 1x and ayj are set to logic "1" and logic ", respectively.
Similarly, the first read amplifier of the main amplifier MAL is set to a high level when the timing signal φra is set to high level and the complementary internal address signals xi and ayj are set to a high level. It is selectively activated by being set to logic “O′” and logic “1”;
The second read amplifier of the main amplifier MAL is selectively activated when the timing signal φra is set to high level and the complementary internal address signals axi and ayj are both set to logic "1". In this operating state,
Each read amplifier has a corresponding read complementary common data line 100L, 10IL or 100R, RIOI.
The binary read signal transmitted through R is further amplified, and the data input/output circuit 110 is transmitted through the read signal line rm.
to communicate. As a result, memory array MARYO or M, AJ? A read signal according to the stored data of one of the two selected memory cells of Y1 is selectively transmitted to the data input/output circuit I10.

The data input/output circuit I10 includes, but is not particularly limited to, a data input buffer sofa and a data output buffer.
and a voltage generation circuit VC including a voltage generation circuit VG.
is selectively brought into operation according to the timing signal φce supplied from the timing generation circuit TG. A timing signal φOe is supplied from the timing generation circuit TG to the data output buffer of the data input/output circuit I10.

The data person cover sofa of the data input/output circuit 110 is Bi
- The CMOS dynamic RAM is set to write mode and the timing signal φC6 is set to a high level, thereby selectively being put into an operating state. In this operating state, the data input cover sofa has the data input/output terminal DIO.
M
It is converted into an OS level write signal and supplied to the main amplifier M A' 0 and the write amplifier of MAI via the write signal line wm.

On the other hand, the data output cover sofa of the data input/output circuit I10 is selectively brought into operation by setting the Bi.CMOS dynamic type RAM in the read mode and setting the timing signal φOe to a high level. In this operating state, the data output cover sofa sends read data outputted via the read signal line rm to the outside via the data input/output terminal DIO.

The timing generation circuit TG forms various timing signals such as a chimble enable signal GE which is supplied as a control signal from the outside, and supplies them to each circuit of the dynamic RAM.

As described above, the Bi/CMOS/C-namic RAM of this embodiment is provided in the address buffer and data input/output circuit I10, and performs a level judgment operation of the address signal or input data supplied at the ECL level. Contains multiple current switch circuits. These current switch circuits each include a constant current source consisting of a bipolar transistor and a resistance means provided on its emitter side, and a voltage generator that supplies a predetermined base voltage vb to the bipolar transistor constituting these constant current sources. Each includes a circuit VG. In this implementation, the voltage generation circuit VG
includes a bipolar transistor Tl provided between its output node ri2 and the circuit ground potential, resistors R2 and R3 provided between the base of this transistor TI and the output node n2 and the circuit ground potential, respectively; The FJ channel MO3FET QI1 is provided between the manual node n1 and the output node n2 and is selectively turned on according to the internal control value qae, and the input node n1 of the voltage generating circuit VG and the circuit A resistor R1 is provided between the input node n1 and the power supply voltage, and a capacitor Ct having a predetermined capacitance is provided between the input node n1 and the ground potential of the circuit. The Bi-cMos dynamic RAM is in a non-selected state and the internal control signal a
When e is set to a low level, the output voltage of the voltage generating circuit VC, that is, the base voltage vb, is set to a low level similar to the ground potential of the circuit, and the capacitor CI is charged to the power supply voltage of the circuit via the resistor R1. When Bl.CMOS dynamic type RAMIJ<selected state and the internal control signal ae is set to high level, the input pressure of the voltage generating circuit VG is temporarily increased by charge sharing. Therefore, the output signal, that is, the base voltage vb, rises rapidly, thereby speeding up the operation of the current switch circuit. As a result, the Bi-CMOS dynamic RAM achieves lower power consumption and faster access time by adopting the power switch method.

As shown in the above embodiment, this invention
By applying the present invention to a semiconductor integrated circuit device such as a MOS dynamic RAM, the following effects can be obtained. In other words, (11) In a Bi/CMOS dynamic RAM that adopts the power switch method, a capacitor with a predetermined capacitance is provided between the input node of the voltage generation circuit and the ground potential of the circuit, and the voltage generation circuit is in the operating state. By temporarily increasing the input voltage at the beginning of the voltage generation circuit, it is possible to achieve the effect that the rise of the output voltage of the voltage generation circuit can be made faster.

(2) Item 11) provides the effect of speeding up the operation of current switch circuits included in address buffers, data input/output circuits, and the like.

(3) According to items (1) and (2) above, B1.
The effect of speeding up the access time of CMOS dynamic RAM, etc. can be obtained.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples (although it is possible to make various changes without departing from the gist of the invention). For example, in FIG. 1, the voltage generation circuit VG may be shared by a plurality of unit address buffers, etc. In this case, in order to increase the driving capability of the voltage generation circuit VC, an output limiter follower circuit may be used. When the voltage generating circuit VC is initially put into operation, if it is necessary to make its input voltage higher than the circuit's power supply voltage, for example, it is effective to add It may also be possible to temporarily boost the MO5FE for the switch.
TQI 1 does not need to be provided on the input side. The specific circuit configuration of the voltage generating circuit VG, the method of temporarily increasing its input voltage at the beginning of the operating state, the voltage value of the base voltage vb, etc. may take various embodiments. In addition, the power supply voltage of the circuit can be set to the ground potential by setting the ground potential side of the circuit to a negative power supply voltage, or the polarity can be reversed by switching the conductivity types of the bipolar transistor and MOSFET. can. In Figure 2, the Bi-CMOS dynamic RAM may have four or more memory arrays, may employ an address multiplex method, and may simultaneously input and output multiple bits of storage data. It is also possible to adopt a so-called multi-bit configuration. The voltage generation circuit VC provided in the data input/output circuit I10 does not need to be selectively put into the operating state, and conversely, the voltage generation circuit 1i18VG provided in the timing generation circuit TG and other circuits is also selectively put into the operating state. Good too. Furthermore, the specific circuit configuration of the row address buffer RAB shown in FIG.
Dynamic type shown in Figure 2! ? Various embodiments can be adopted, such as the AM block configuration and combinations of each control signal 9- and address signals.

The above explanation mainly describes the invention made by the present inventor in BL/CMOS, which is the application field that became the 7J's vision.
Although we have explained the case where it is applicable to dynamic RAM, it is not limited thereto. For example, Bt-C
The present invention can also be applied to MOS static RAMs, various other semiconductor storage devices, and logic integrated circuits with built-in memories. Can be widely used.

(Effects of the Invention) The effects obtained by typical inventions disclosed in this application are as follows.In other words, the Bi- In a CMOS dynamic RAM, for example, a capacitor with a predetermined capacitance is provided between the input node of the voltage generation circuit and the ground potential of the circuit, and the input voltage is temporarily set when the voltage generation circuit is put into operation. By increasing the power supply voltage, the rise of the output voltage can be made faster.This can speed up the operation of current switch circuits included in address buffers, data input/output circuits, etc. Bl/CM OS dynamic type R while aiming for low power consumption
Access time for AM, etc. can be sped up.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a row address buffer 1 of a B t -CMOS dynamic RAM to which the present invention is applied, and FIG.
FIG. 3 is a block diagram showing an embodiment of the CMOS dynamic RAM; FIG. 3 is a signal waveform diagram showing an embodiment of the Bt' CMOS dynamic RAM of FIG. 2; and FIG. Bi/CMOS developed by the inventors
Signal waveform diagram showing an example of dynamic RAM, 5th r:! Je;t:, Fig. 4 (7) B l ・CMO
FIG. 5 is a circuit diagram showing an example of a row address buffer of a 5l'4+i y type RAM. RAB...Row address buffer, TS...Timing setting circuit, DABO...Unit address buffer,
DLI~DL2...delay circuit, IC...input circuit,
C3...Current switch circuit, VG-...Voltage generation circuit, GXP, GXN. GRP, GRN...gate circuit, LP, LN...latch circuit, ADP, ADN...address driver, Q
1~Q2...P channel MO3FETSQl 1~
Q12...N channel MO3FET%T1~Tll
...NPN type bipolar transistor, N'l~N6
...CMOS inverter circuit, NAGI~NAG2・
...Nant gate circuit, N001-N0G3...Nor gate circuit, D1-D2...Diode, 01-C3
... Capacitor, Cs... Parasitic capacitance, R1 to R6.
··resistance. MARYO, MARYI...Memory array, 5APO
, 5AP1.5ANO, 5ANI... sense amplifier,
C3O, C5I... Column switch, CAD... Column address decoder, RADO, RADI... Row address decoder, PCAD... Bri column address decoder, PRAD... Bri row address decoder,
CAB...Column address buffer, RAB...Row address buffer, RFC...Refresh. Address counter, MAO, MAI...main amplifier, Ilo...data input/output circuit, TG...timing generation circuit.

Claims (1)

[Claims] 1. A voltage generating circuit is provided which is selectively brought into an operating state according to a predetermined control signal and forms a predetermined output voltage based on a predetermined input voltage, and the voltage generating circuit is in an operating state. A semiconductor integrated circuit device characterized in that the absolute value of the input voltage is temporarily increased at the beginning of the input voltage. 2. The voltage generating circuit has a first bipolar transistor provided between its output node and the ground potential of the circuit, and a base of the first bipolar transistor and the output node and the ground potential of the circuit. The device includes first and second resistor means provided respectively, and a switch means provided between the input node and the output node and selectively turned on according to the control signal, the switch means being selectively turned on according to the control signal, A third resistance means is provided between the node and the power supply voltage of the circuit, and a capacitor having a predetermined capacitance is provided between the input node and the ground potential of the circuit. A semiconductor integrated circuit device according to claim 1. 3. The semiconductor integrated circuit device is a Bi-CMOS dynamic RAM, and the voltage generation circuit is the B
When the i-CMOS dynamic RAM is brought into a selected state, a predetermined base voltage is selectively supplied to the second bipolar transistor constituting the constant current source of the address input circuit. A semiconductor integrated circuit device according to claim 1 or 2.