JPS6325880A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To convert efficiently a level by amplifying one side ECL level signal with an amplifying circuit having a large gain composed of a driving MOSFET and a constant current source and driving a CMOS push-pull output circuit. CONSTITUTION:From the collector of differential amplifying transistors T2 and T3 of an input circuit IB, a complementary ECL level signal is supplied to the gate of P channels MOSFET Q15 and Q16, and to the gate of an N channel MOSFET Q18 which is made into the serial mode with the MOSFET Q16, and an output signal P1 of the inverting amplifying circuit composed of the MOSFET Q15 and a load MOSFET Q17 is supplied. The P channel MOSFET Q16 and the N channel MOSFET Q18 constitute a complementary push-pull output circuit. Thus, since the large voltage gain can be obtained, the desired level-converted output signal can be efficiently obtained without increasing the consumption current.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, in which, for example, a peripheral circuit includes an ECL circuit and a memory array is 0M.
Static type RAM configured by 03 circuit (
It relates to techniques that are effective for use in random access memory (random access memory).

[Conventional technology]

A CMOS in which CMOS static RAM (Random Access Memory) is directly accessed by an ECL (emitter coupled logic) circuit.
-E CL compatible RAM is
Digest Op Technical Papers (ISS
CDIGII! ST OF TECHNICAL PAP
ERS) magazine, February 1982, pp248-24
9. In addition, in order to increase the speed of CMOS static type RAM, one using bipolar type transistors was proposed in Japanese Patent Application Laid-open No. 56-58193, Nikkei McGraw-Hill Publishing, "Nikkei Electronics", May 21, 1984, page 198, etc. ing.

[Problem that the invention seeks to solve]

The static RAM as described above requires a level conversion circuit that converts an ECL level, which has a relatively small signal amplitude, to a CMOS level, which has a relatively large signal amplitude. Furthermore, in order to store data by upgrading the static RAM to a battery bank, it is necessary to reduce current consumption in a chip non-selected state.

An object of the present invention is to provide a semiconductor integrated circuit device equipped with a level conversion circuit that converts a small signal amplitude into a large signal amplitude with a simple configuration.

Another object of the present invention is to provide a semiconductor integrated circuit device that includes an ECL circuit and a CMOS circuit and has reduced current consumption on the ECL circuit side when a chip is not selected.

Still another object of the present invention is to provide a semiconductor integrated circuit device that suppresses an increase in current consumption as the power supply voltage increases.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, one of the complementary ECL level input signals is amplified by an amplifier circuit consisting of a drive MOSFET and a load MOSFET that operates as a constant current source, and this output signal and the other ECL level input signal are amplified. The signal is supplied to a complementary push-pull MO3 output circuit to form a CMOS level signal. Further, the constant voltage supplied to the gate of the constant current MOSFET is supplied to the source by a forward voltage formed by a bipolar transistor in the form of a diode, and is formed by a voltage dividing resistor provided between the drain and the operating voltage. A MOS FET whose gate is supplied with a divided voltage forms a constant voltage that is less dependent on the power supply and outputs it through an emitter follower output circuit.

[For production]

According to the above-mentioned means, one ECL level signal is amplified by an amplifier circuit with a large gain consisting of a drive MOSFET and a constant current source to drive a CMOS push-pull output circuit, so level conversion can be performed efficiently. It can be carried out. In addition, the above voltage dividing resistor allows MOS F E
By applying feedback to the gate voltage of T, it is possible to form a constant voltage that is not affected by fluctuations in the power supply voltage.

[Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment in which the present invention is applied to a static RAM formed by Bi-CMO3 technology. Although not particularly limited, the RAM shown in the figure is formed on a single semiconductor substrate such as single crystal silicon using known integrated circuit technology. In the figure, the P-channel MOSFET is distinguished from the N-channel MOSFET by adding an arrow to its channel (back gate).

Although not particularly limited, this embodiment is directed to a static RAM that is compatible with ECLRAM. Therefore, the power supply voltage is a negative voltage -Vee
is used.

One specific circuit of the memory cell MC is shown as a representative, and is an N-channel storage MOSFETQ.
1. The gate and drain of Q2 are cross-wired together. Although not particularly limited, between the drains of the MOSFETs QI and Q2 and the power supply voltage Vcc, there are high resistances R1 and R formed of a polysilicon layer for information retention.
2 is provided. Above MOSFETQ1. An N-channel transmission gate MOSFET Q3.Q2 is connected between the common connection point of Q2 and the complementary data iDo, Do. Q4 is provided. Other memory cells MC also have similar circuit configurations. These memory cells are arranged in a matrix. The gates of the transmission gate MOSFETs Q3, Q4, etc. of the memory cells arranged in the same row are commonly connected to the corresponding word lines WO, Wn, etc. shown by way of example, and the inputs of the memory cells arranged in the same column are connected in common to the corresponding word lines WO, Wn, etc. The output terminal is
A pair of corresponding complementary data lines (bit lines or deshift lines) Do, DO and Di, each illustratively shown;
Connected to Dl etc.

In the memory cell MC, in order to make it consume low power, the resistor R1 can maintain the gate voltage of MOS FETQ2 above the threshold voltage when MOS FETQl is turned off. The resistance value is set to a certain level. Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistor R1 is the MOSFET QI
The information stored in the gate capacitance (not shown) of MOSFET Q2 due to the drain leakage current of ! i! It is designed to have a current supply capacity sufficient to prevent charges from being discharged.

Although not particularly limited, an N-channel load MOS
FETQ5. Q6 is provided. Complementary data line DI is shown as another representative.

A similar MOSFET Q7 is also used for Dl. Q8 is provided.

In the figure, the word line WO is connected to the X address decoder
The selection is made by the output signal formed by the NOR gate circuit G1 forming the DCR. This also applies to other word lines Wn.

The X-address decoder XDCR is configured by mutually similar NOR gate circuits G1.02 and the like. The input terminals of these NOR gate circuits Gl, 02, etc. receive an external address signal AO- consisting of multiple bits as described later.
Internal complementary address signals formed by an X address buffer XADB receiving At (address signals output from an appropriate circuit device not shown) are applied in a predetermined combination. Note that each unit circuit of the X address decoder XDCR is one NOR gate circuit Gl.

62, etc., but in order to reduce the number of gates in the entire address decoder and to reduce parasitic input capacitance, it is desirable to configure the address decoder by dividing it into multiple stages, such as by arranging a pre-decoder. .

A pair of complementary data lines DO, D in the memory array
o, Di, and Di are transmission gate MOSFETQ9. QIO and Qll, G12
It is connected to the common complementary data lines CD, CD through a column switch circuit composed of the following.

MOSFETQ9 that constitutes the above column switch circuit.
A selection signal formed by a Y address decoder YDCR is supplied to the gates of QIO, Qll, and G12, respectively. This Y address decoder YDCR is a mutually similar NOR gate circuit G3. Consists of G4 etc.

These NOR gate circuits G3.04, etc. have an internal complementary address formed by a Y address buffer Y-ADB that receives an external address signal AO=Aj (address signal output from an appropriate circuit device not shown) consisting of multiple bits. Signals are applied in a predetermined combination.

The common complementary data lines CD and CD are connected to the readout circuit R.
It is connected to the input terminal of A and the output terminal of write circuit WA. The readout circuit RA includes a common complementary data line CD,
A sense amplifier that amplifies the CD read signal and an ECL
It includes an output circuit and sends out an ECL level read signal to the output terminal Dout. The write circuit WA has an input terminal D
The write data signal at the ECL level inputted from the in is amplified to form a write signal at the CMOS level and sent to the common complementary data lines CD, CD.

The timing control circuit TC receives control signals from external terminals WE and C8, and forms various timing signals such as the operation M open signal for the read circuit RA and write circuit WA.

The above X address buffer XADB is one of the circuits (
unit circuit) is shown as a representative.

That is, the address signal from the external terminal AO is transmitted through the bipolar transistor T1 and the level shift diode D1.
and a MOSFE as a current source that forms its operating current.
The signal is supplied to the next ECL circuit via an emitter follower circuit consisting of TQ13. The ECL circuit includes differential transistors T2. T3 and MOSFET Q14 as a current source provided at its common emitter and forming its operating current.
and the differential transistor T2. It is composed of load resistors R3 and R4 provided at the collector of T3.

MOSFETQ13 as the above current source. G14 operates as a constant current source by having its gate supplied with a constant voltage VB from a voltage generation circuit, which will be described later. The output signal of the emitter follower circuit is supplied to the pace of the one differential transistor T2, and the reference voltage vbb as a logic threshold voltage is supplied to the base of the other differential transistor T3. Each of the above circuit elements constitutes an input circuit IB.

Complementary ECL level signals are sent out from the collectors of the differential amplification transistors T2 and T3 of the input circuit TB. A complementary signal at the ECL level consisting of an address signal in the same phase as the address signal supplied from the external terminal AO and an address signal in the opposite phase is converted to the CMOS level by the next level changing circuit LVC. The complementary signal is applied to P-channel MOSFETQ15. Supplied to the gate of G16.

MOSFETQ15 that receives one ECL level signal
A load MOSFET Q17 that operates as a constant current source by receiving the constant voltage VB is provided at the drain of the MOSFET Q17. The gate of the N-channel MOSFET Q18 connected in series with the MOSFET Q16 has a
The output signal PL of the inverting amplifier circuit consisting of the MOSFET Q15 and the load MOSFET Q17 is supplied. Thereby, the P-channel MOSFET Q16 and the N-channel MOSFET QI8 constitute a complementary push-pull output circuit.

Here, the inventors of the present application first developed the constant current source Mo5FE.
Instead of TQ17, MOSFETQ17 was diode-connected, and MOSFETQ18 was considered to be in a current mirror configuration. However, in such an MO3 amplifier circuit, since complementary signals having opposite phases to each other are supplied to the gates of the P-channel Mo SF ETQ15 and Q16, the MO3FBTQ15. The drain current of Q16 flows differentially. For example, when the current in MOSFET QI 5 is made relatively large, the current in MOSFET QI 6 is made relatively small. In this case, the above MOSFETQ
A large current flows through the MOSFE in the form of a current mirror.
Since it is supplied to MOSFETQ17, the conductance of this MOSFETQ17 increases and acts to reduce its voltage gain. This prevents efficient level conversion operations. In contrast, in this embodiment, by using the load MOSFET that operates as the constant current source, a large voltage gain can be obtained without increasing the current consumption (desired level-converted output Signals can be obtained efficiently.

Although not particularly limited, an address signal (N2
) to form MOSFETs Q19 to Q similar to the above.
A level conversion circuit constituted by 22 is provided. MOSFETQ19, which is the human power of this level conversion circuit. Q
20 is supplied with a complementary signal at a BCL level that is in opposite phase to that in the above case.

In this embodiment, the following output circuit OB is provided in order to drive at high speed a load capacitance having a relatively large capacitance value consisting of the input capacitances of a large number of gate circuits constituting the address decoder. That is, one output signal N1 of the complementary signals formed by the level conversion circuit LVC is
It is supplied to the base of bipolar NPN output transistor T4. This output transistor T4 is responsible for charging the capacitive load, and a similar output transistor T5, connected in cascade with the output transistor T4, is responsible for discharging the capacitive load. In order to operate this output transistor T5 complementary to the output transistor T4, a MOS is connected between the base and collector of the transistor T5.
FETQ23 is provided. The gate of this MOSFETQ23 is connected to the MOSFET of the level conversion circuit LVC.
A signal P1 is supplied which is generated at the drain of Q17 and is supplied to the gate of MOSFET Q18. A MOSFET Q24 receiving the output signal aO is provided between the base of the output transistor T5 and the negative power supply voltage -Vee.

An output circuit that forms an output signal τO having a phase opposite to the output signal aO is also a transistor T6 similar to the above. T7 and MOSF
ETQ25. Consists of Q26. However, the base of the output transistor T6 that charges the capacitive load is supplied with the other level-converted output signal N2, and the MOSFET Q25 provided between the base and collector of the output transistor T7 that discharges the capacitive load is supplied with the other level-converted output signal N2. At the gate of
A level conversion output signal P2 generated at the drain of the level conversion circuit LVC(7) MOSFET Q21 is supplied.

The operation of this output circuit OB is as follows.

When the one level-converted output signal N1 is at a high level (ground potential of the circuit), the output transistor T4 is turned on and the output signal aQ is set at a high level. At this time, the level conversion output signal P1 is at a low level (negative power supply voltage -V
ee), MOSFET Q23 is turned off, and the high level of the output signal aO turns the MOSFET Q23 off.
TQ24 is turned on. Above MOSFETQ24
Due to the on state of T5, a low level is supplied to the base of the output transistor T5. This turns the output transistor T5 off. Therefore, the capacitive load is quickly charged, and the output signal aO is quickly charged to a high level.

From the above state, when the one level conversion output signal changes to Nl low level and the level conversion output signal P1 changes to high level, the output transistor T4 is turned off by the low level of the level conversion output P1. Due to the high level of the other level conversion output signal N2, M
OSFETQ23 is turned on. This MOSFE
Due to the on state of TQ23, the high level of the output signal aO is supplied to the base of the output transistor T5, thereby turning on the output transistor T5. In other words, due to the ON state of MOSFET Q23, the base and collector of the output transistor T5 are connected, so that the output transistor T5 becomes a diode and discharges the high-level output signal aO at a true speed. At this time, due to the high level of the output signal aO, -1τ03FETQ24
is turned on, but the MOSFET
By setting its conductance smaller than that of Q23, it is possible to prevent the ON operation of the output transistor T5 from being inhibited.

The operation of the output circuit that forms the output signal TO having the opposite phase to the output signal aO is different from that in the above case because the level-converted output signal is supplied with the opposite phase.
6. T7 is controlled on/off in reverse.

Note that in order to prevent the output transistor T5 from being driven in the saturation region, the drain of MOSFET Q23 is connected to the collector of the transistor T5 instead of the circuit ground potential, and similarly prevents the transistor T7 from being driven in the saturation region. Therefore, the drain of Mo5FETQ65 is connected not to the ground potential of the circuit but to the collector of transistor T7. , thereby speeding up the switching operation.

In this embodiment, by using a bipolar transistor with a large current driving capacity in the output section of the address buffer, a relatively large capacitance such as a gate capacitance is added to the gates of many MOSFETs that constitute the address decoder as a load. It is possible to charge/discharge the parasitic capacitance that has been set to a value at high speed. Such an output circuit OB is
Although not shown, the address decoder XD in FIG. 1 above
By also providing the output section of CR, YDCR, or the output section of the pre-decoder, it is possible to speed up the selection operation of the memory array.

Note that MOSFETQ23 (Q
25), the gate of MOS FETQ 15 (Q1
9) that directly supplies the drain output, or Mo
The level conversion circuit consisting of 5FETQ69 to Q22 is omitted, and the other level conversion output N2 is converted to Mo5FETQ.
It may be directly obtained from the drain side of 65.

In this embodiment, the input circuit IN in the address buffer XADB and the constant current MO in the level conversion circuit
The constant voltage VB supplied to the S FET is formed by the following constant voltage circuit.

The constant voltage circuit improves power supply dependence, in other words, prevents the current consumption in the address buffer ADB from increasing due to a change in the constant voltage VB as the power supply voltage increases. The following circuit is used for this purpose.

The source of Mo5FETQ6 is connected to the negative power supply voltage -vbb
is level-shifted and supplied by the forward voltage of the diode D2, which is a bipolar transistor. Voltage dividing resistors R5 and R6 are provided between the drain of this Mo5FETQ6 and the ground potential point of the circuit. The divided voltage at the connection point of this voltage dividing resistor R5 and R6 is the voltage of the MOSFETQ
6 is supplied to the game I-. And the above MOSFET
The drain voltage of Q6 is the bipolar transistor T8.
MO3F ETQ operates as a resistance means by constantly supplying the ground potential of the circuit to its gate.
The signal is output via an emitter follower output circuit consisting of 8. As a result, the constant voltage V'B is
The voltage drop at is made equal to the voltage.

In this embodiment, for example, when the power supply voltage -vbb increases in absolute value and the current flowing through resistors R5 and R6 attempts to increase, the divided voltage according to the resistance ratio decreases in absolute value and the voltage of Mo5FET Q6 increases. fl'Jiff is applied so that the conductance becomes small. This compensates for the variation in the drain voltage of the MOS FETQ 6 with respect to the variation in the power supply voltage -vbb. The above resistance R
By setting the resistance ratio R5/R6 between R5 and R6 to approximately 4/1, it is possible to obtain a constant voltage that is not affected by fluctuations in the power supply voltage -vbb. By forming a constant voltage VB that is constant against such fluctuations in the power supply voltage -vbb, the minimum necessary constant current corresponding to the desired operating speed can be maintained at the above address without considering fluctuations in the power supply voltage -vbb. It can be configured to flow to the buffer ADB.

[Embodiment 2] FIG. 2 shows a circuit diagram of an embodiment of an output circuit of a static RAM that is compatible with the TTL level.

As the operating voltage of the RAM in this embodiment, a positive power supply voltage Vcc is used in order to adapt it to the TTL level.

As the sense amplifier SA that receives the read signal from the memory array M-ARY, a differential amplifier circuit configured with bipolar transistors is used. Therefore, a read signal having a relatively small signal amplitude, such as the ECL level, is sent out from the sense amplifier SA. For this reason, the output circuit is also provided with a pair of level conversion circuits made up of MOSFETs Q31 to Q38 similar to the level conversion circuit shown in FIG. 1 above. One of the level-converted outputs is supplied to the base of a bipolar output transistor Tll provided on the power supply voltage side. The emitter of this transistor Tll is provided with a level shift circuit constituted by a transistor T10 in the form of a diode in order to obtain a high level adapted to the TTL level. The other level-converted output is supplied to the gate of an output MOSFET Q42 provided on the ground potential side of the circuit. As a result, the transistor T11 and the MOS
By FETQ42 performing push-pull operation,
An output signal conforming to the TTL level is sent out from the output terminal Dout.

Further, in order to cause the output circuit to be USed by the output control signal DOC and create an output high impedance state, the control signal D is connected between the base of the transistor Tll, the gate of the MOSFET Q42, and the ground potential point of the circuit.
Switches MO3FF, TQ40 and Q41 receiving OC are provided, respectively. When the control signal DOC is set to high level, the MOSFETs Q40 and Q41 are turned on, and the transistors Tll and MOSFETQ are turned on.
42 are both turned off, and the output terminal Dout is placed in a high impedance state. At this time, in order to prevent wasteful current consumption in the level conversion circuit, the above-mentioned combinatory floating output MOSFET Q33. Q
34 and Q37. Q38 is a P-channel power switch MOSFET Q3 that receives the control signal DOC.
The operating voltage is supplied via 9. In the above output high impedance state, P channel MOS FETQ
39 is turned off to prevent the above-mentioned wasteful current consumption.

Further, among the above output circuits, the operating voltage of the push-pull output circuit that forms drive signals for the output transistor Tll and the output MOSFET Q42 is the tillit voltage Vcc' supplied by an independent power supply wiring.The reason for this is as follows. Since a relatively large operating current flows in address buffers, sense amplifiers, etc., if the power supply wiring is the same as that of the other internal circuits, the internal power supply voltage will drop relatively significantly due to the wiring resistance. This is because if there is such a decrease in the operating voltage level, the high level sent out from the output terminal Dout will also decrease, reducing the margin for the TTL high level.

Further, in order to drive a relatively large load connected to the external terminal Dout, the output transistor Tll is configured to allow a relatively large current to flow.

By separating the power supply line as described above, it is possible to reduce noise generated on the power supply line when the transistor Tll passes the drive current from being transmitted to other internal circuits.

Further, in this embodiment, the constant voltage VB of the constant voltage circuit similar to that shown in FIG. 1 is outputted through the switch MOSFETQ29. A chip selection signal is supplied to the gate of this MOS FETQ29.

A switch MOS is connected between the output side of the MOSFET Q29 and the ground potential point of the circuit, which is controlled by the output signal of the inverter circuit N1 which receives the chip selection signal CS.
FETQ30 is provided.

As a result, when the chip selection signal C8 is set to low level and the chip is not selected, the switch MOSFET
Since Q29 is turned off and switch MOSFET Q30 is turned on, the constant current MOSFET Q32.3
A low level is supplied to gates such as No.6. This causes constant current MOSFET Q32. Q36 etc. are turned off, and the current consumption in the chip non-selected state can be significantly reduced. Although not shown, the output voltage VB of the constant voltage circuit is commonly supplied to the gates of other constant current MOSFETs constituting the address buffer and the sense amplifier. In this way, when the chip is not selected,
In particular, when the power to the device is cut off, it is possible to use the battery to retain data in the RAM.

[Embodiment 3] FIG. 3 shows a circuit diagram of another embodiment of a constant voltage circuit.

In this example, MO3F]E in diode form
Chip selection signal C8 is supplied from an external terminal to the gate of MOSFETQ44 that supplies bias current to TQ43 and bipolar transistor T9 (diode D2).
The output signal of the inverter circuit N2 receiving the signal is supplied.

As a result, in the chip selection state in which the chip selection signal C8 is set to low level, the MOSFET Q44
M in the form of a diode acts as a resistive means.
A bias current is supplied to OSFETQ43 and bipolar transistor T9. This allows MOSFETQ
From the drain of 43, a bipolar transistor T9
A constant voltage is obtained by the voltage between the base and emitter of MOSFETQ43 and the voltage between the gate and source of MOSFETQ43. This constant voltage is connected to the same transistor T8 and MOSFET Q2B as above.
By outputting through an emitter follower output circuit consisting of the gate of MOSFET Q43.

A constant voltage VB is formed according to the source-to-source voltage (threshold voltage). In this embodiment, when the chip is brought into a non-selected state, MOSFET Q44 is turned off, so that no current flows through the series circuit of MOSFETs Q44, Q43 and transistor T9. As a result, the transistor T8 is also turned off because the base current no longer flows. As a result, it is possible to prevent current consumption in the constant voltage circuit from occurring in the chip non-selected state. Also,
The output voltage VB is a MOSFET that operates as a resistance element.
Q28 sets it to a low level like the ground potential of the circuit. Therefore, as described above, current consumption in the address buffer, sense amplifier, and output circuit can be significantly reduced.

In this example circuit, a switch operation is performed by a MOS FET that supplies a bias current to the constant voltage generating circuit. The JtL configuration eliminates the current consumption of the constant voltage circuit itself.

Note that compensation for power supply voltage fluctuations as described above can be realized by replacing the resistors R5 and R6 with MOSFETs controlled by the chip selection signal as described above.

The effects obtained from the above examples are as follows.

(1) One of the complementary ECL level input signals is amplified by an amplifier circuit consisting of a load MOS FET that operates as a drive MOS FET constant current source, and the output signal and the other ECL level are amplified. input signal and P
Channel MOSFET and N-channel MOSFET
By supplying the signal to a push-pull output circuit consisting of T, an effect can be obtained in that a very efficient level conversion operation can be performed with low current consumption.

(2) When sending the output signal of the push-pull output circuit to an external terminal as a TTL level output signal, the desired level margin can be achieved by supplying the operating power supply voltages of the push-pull output circuit and the output circuit from independent power lines. In addition to being able to obtain an output signal having a high current level, it is also possible to reduce the transmission of noise generated when the output circuit operates to the power supply line of the internal circuit.

(3) Load MOS F E that operates as the above constant current source
When the semiconductor integrated circuit device is in the non-selected state, T is turned off according to the actual chip selection signal, thereby achieving the effect that the current consumption in the non-selected chip state can be significantly reduced.

(4) A load MOS whose switch is controlled by a substantial chip selection signal for the constant voltage element that forms the constant voltage.
By supplying the bias current through the FET, it is possible to reduce the current consumption of the constant voltage circuit itself in the chip non-selected state.

(5) As a constant voltage circuit, the forward voltage of the diode is supplied to the source, the voltage dividing resistor is provided between the drain and the operating voltage, and the divided voltage formed by this voltage dividing resistor is supplied to the gate. By using a MOSFET and appropriately setting the resistance ratio of the voltage dividing resistor, it is possible to obtain a constant voltage that compensates for source dependence. As a result, it is possible to set the constant current to the minimum necessary to achieve the desired signal transfer characteristics without considering power supply fluctuations, thereby achieving the effect of reducing power consumption and increasing speed as a whole.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, memory cells include the so-called HiCMO3 type that uses the high resistance mentioned above, as well as P
It may be a complete 0MO3 type consisting of an inter-channel O5FET and an N-channel MOsFET.

The present invention can be widely used in various semiconductor integrated circuit devices such as a gate array constructed of a combination of a TTL circuit, an ECL circuit, and a CMO3 circuit, in addition to the static type RAM described above.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, one of the complementary ECL level input signals is amplified by an amplifier circuit consisting of a load MOSFET that operates as a driving MOSFET constant current source, and the output signal and the other ECL level input signal are amplified. By supplying the signal to a push-pull output circuit consisting of a P-channel MO8FET and an N-channel MOSFET, an efficient level conversion operation can be performed with low consumption. In addition, as a constant voltage circuit for operating the load MOSFET at a constant current, the forward voltage of the diode is supplied to the source, and a voltage dividing resistor is provided between the drain and the operating voltage, and a voltage dividing resistor is formed by this voltage dividing resistor. By using a MOSFET whose gate is supplied with a divided voltage, and by appropriately setting the ratio of the resistances of the voltage dividing resistors, it is possible to obtain a constant voltage that compensates for dependence on the power supply.

[Brief explanation of drawings]

Figure 1 shows a static RAM to which this invention is applied.
FIG. 2 is a circuit diagram showing one embodiment of an output circuit that forms a TTL level output signal. FIG. 3 is a circuit diagram showing another embodiment of a constant voltage circuit. It is a diagram. XADB...X address buffer, YADB...Y address buffer, XDCR...X address decoder, YD
CR...Y address decoder, MC...memory cell, W
A: Write circuit, RA: Read circuit, TC: Timing control circuit, IB: Input circuit, LVC: Level conversion circuit, OB: Output circuit Patent attorney Katsuma Ogawa ->,.

Claims (1)

[Claims] 1. A drive MOSFET that receives one of the complementary ECL level input signals, and this drive MOSFET.
A load M that operates as a constant current source provided at the drain of
A level conversion circuit including an amplifier circuit including an OSFET, and a push-pull output circuit including a P-channel MOSFET and an N-channel MOSFET that receive the output signal of the amplifier circuit and the other ECL level input signal. Semiconductor integrated circuit device. 2. The output signal of the push-pull output circuit is transmitted to the input of an output buffer that includes an emitter follower output transistor and a level shift diode and forms a TTL level output signal and sends it to an external terminal. 2. The semiconductor integrated circuit device according to claim 1, wherein the operating power supply voltages of the output buffer and the output buffer are supplied from independent power supply lines. 3. The load MOSFET that operates as the constant current source is:
3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is turned off in accordance with a substantial chip selection signal when the semiconductor integrated circuit device is in a non-selected state. 4. The constant voltage that causes the load MOSFET to operate as a constant current source is generated by a load MOSFET whose switch is controlled by a substantial chip selection signal, and a diode configured by a bipolar transistor to which a bias current is supplied from the load MOSFET. Claim 3, characterized in that the device comprises a series circuit consisting of a diode constituted by a MOSFET, and an emitter follower output circuit that receives a constant voltage in the forward direction formed by these two diodes. semiconductor integrated circuit devices. 5. In the semiconductor integrated circuit device, the memory cell is a MOSF
Claim 1, characterized in that the RAM is constituted by a static type circuit constituted by an ET, and the peripheral circuit that transmits and receives signals with at least an external terminal is a static type RAM constituted by a bipolar transistor. , the semiconductor integrated circuit device according to the second, third, or fourth item. 6. The forward voltage of a diode constituted by a bipolar transistor is supplied to the source, and the voltage divider resistor provided between the drain and the operating voltage, and the voltage divider formed by this voltage divider resistor, are supplied to the gate. MOS supplied
FET, and an emitter follower output circuit that receives the drain voltage of the MOSFET, and includes a constant voltage generation circuit that compensates for the power supply dependence of the drain voltage of the MOSFET by appropriately setting the resistance ratio of the voltage dividing resistor. A semiconductor integrated circuit device characterized by: 7. The constant voltage generated by the constant voltage generation circuit is applied to a drive MOSFET that receives one of the complementary ECL level input signals and a load MOSF that operates as a constant current source provided at the drain of this drive MOSFET.
ET, and a push-pull output circuit consisting of a P-channel MOSFET and an N-channel MOSFET that receive the output signal of this amplifier circuit and the other ECL level input signal. 7. The semiconductor integrated circuit device according to claim 6, wherein the semiconductor integrated circuit device is supplied to the gate of a constant current MOSFET of the circuit that forms the ECL level signal.