JPS60231349A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPS60231349A JPS60231349A JP59088165A JP8816584A JPS60231349A JP S60231349 A JPS60231349 A JP S60231349A JP 59088165 A JP59088165 A JP 59088165A JP 8816584 A JP8816584 A JP 8816584A JP S60231349 A JPS60231349 A JP S60231349A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- lead part
- lead frame
- inner lead
- adhesion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（発明の技術分野）
この発明は半導体、ペレット等を収納するパッケージに
係り、特にプラスチックパッケージに使用されるリード
フレームに関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a package for accommodating semiconductors, pellets, etc., and particularly to a lead frame used in a plastic package.
一般に集積回路等のプラスチックパッケージ製品の耐湿
性を定める要因としては、
■ 半導体素子自体特にそのパッシベーション膜等、
■ プラスデックモールド樹脂の不純物含有量（ＣＩ−
イオン等）、
■ モールド樹脂の吸湿、透湿性、リードフレームどの
密着性、
■ 半導体素子の外部汚染等が挙げられる。In general, the factors that determine the moisture resistance of plastic package products such as integrated circuits are: ■ The semiconductor element itself, especially its passivation film, etc.; ■ The impurity content of the Plus Deck molding resin (CI-
(ions, etc.), (2) moisture absorption and permeability of mold resin, adhesion of lead frames, (2) external contamination of semiconductor elements, etc.
この中で、半導体素子を形成するアルミ配線の腐蝕を直
接引き起こす水分の侵入に対しては種々の対策が採られ
ている。これはリードフレームと樹脂との密着性を試験
するラジフロにＪ：る試験結束どプレッシャークックテ
スト（ＰＣＴという）等の寿命試験結果との間に相関が
見られるという報告もあるためである（トリケッブス発
行、１〜す’ｙｙ７）、１）Ｌｔ−ヘーハースＮｏ１２
１ＳＴＶＬＳＩパッケージング技術、第７章パッケージ
ング実例と信頼性評価参照）。このにうに従来は樹脂の
密着性や気密性を上げるためにモールド技術あるいは樹
脂の検討がおこなわれていた。Among these, various measures have been taken to prevent moisture from entering, which directly causes corrosion of aluminum wiring forming semiconductor elements. This is because there are reports that there is a correlation between the results of life tests such as the Pressure Cook Test (PCT), which tests the adhesion between lead frames and resin. Published, 1-S'yy7), 1) Lt-Hehers No. 12
1STVLSI packaging technology, see Chapter 7 Packaging Examples and Reliability Evaluation). In order to improve the adhesion and airtightness of resins, molding techniques or resins have been investigated in the past.
ところで、密着性あるいは気密性の向上に関しては、パ
ッケージ内に封入されるリードフレームがもう１つの大
きな要因となっているが、これについては従来あまり考
慮が払われていなかった。Incidentally, the lead frame enclosed within the package is another major factor in improving adhesion or airtightness, but little consideration has been given to this in the past.
従来プラスチックパッケージ用のリードフレーム材質と
しては、主として４２７０イ銅系合金材利が使用されて
きたが、これは機械的強電、熱伝導性、熱膨張係数、メ
ッキ性、コスト等、半導体素子とのマツチングや干−ル
ド樹１ｉｆｔどのマップ−ングを考慮して決定されたも
のである。しかしパッケージ内に収納されるリードフレ
ームの表面についてはとくに考慮されているものは無か
った。Traditionally, 4270I copper-based alloy material has been mainly used as lead frame material for plastic packages, but this material has poor mechanical strength, thermal conductivity, coefficient of thermal expansion, plating property, cost, etc. This was determined by considering mapping such as matching and dry tree 1ift. However, no particular consideration has been given to the surface of the lead frame housed within the package.
第１図は従来広く使用されているリードフレームの構造
を示１一平面図である。ペレット塔載部１に半導体素子
等のペレッ］〜が塔載され、この塔載部１に一端が近接
した複数のリード２が配列されている。ペレッ１へ塔載
部１に半導体素子をダイボンドし、この半導体素子とリ
ード２との間でワイ翫７−ボンドが終了したのち、プラ
スチック樹脂対１１にＪ：り図中に２点鎖線で示した部
分３内がパッケージ内に収納される。FIG. 1 is a plan view showing the structure of a conventionally widely used lead frame. Pellets such as semiconductor devices are loaded on a pellet loading section 1, and a plurality of leads 2 with one end adjacent to the pellet loading section 1 are arranged. A semiconductor element is die-bonded to the mounting part 1 of the pellet 1, and after the wire 7-bonding is completed between the semiconductor element and the lead 2, the plastic resin pair 11 is bonded to the plastic resin pair 11 as shown by the two-dot chain line in the figure. The inside of the portion 3 is stored in the package.
なお、この−［−ルド樹脂パッケージ内（部分３内）に
存在するり一ド２の部分をインナーリード、その外部に
突出するリード２０部分をアウターリードど呼んでいる
。アウタリードはタイバー４に接続され、このタイバー
４はリードフレーム５に結合してリードフレームの中位
ユニツ１−が形成されている。It should be noted that the portion of the lead 2 existing within the -[--led resin package (within the portion 3) is called the inner lead, and the portion of the lead 20 protruding to the outside thereof is called the outer lead. The outer lead is connected to a tie bar 4, which is coupled to a lead frame 5 to form a middle unit 1- of the lead frame.
この場合従来のリードフレームでは、リードフレームの
表面を特に配慮をしたものはない。強いて挙げれば、前
述したダイボンドやワイヤボンドのためにリードフレー
ムの全面をメッキするものや、ボンディングエリアのメ
ッキ厚を保持するためにボンデインクエリアよりやや広
めに第１図で点線で囲んだ領域６内を部分メツ４−シた
１〕のがあるにすぎない。In this case, none of the conventional lead frames takes particular consideration to the surface of the lead frame. To name a few, the entire surface of the lead frame is plated for die bonding or wire bonding as described above, and the area 6 surrounded by the dotted line in Figure 1 is slightly wider than the bonding ink area in order to maintain the plating thickness of the bonding area. There is only 4 parts of the inside.
これらのメッキはプラスチックパッケージを形成するモ
ールド樹脂どの密着性を考慮してなされたものではない
。今１１１ＳＴ、ＶＩＳＩ化が進むとパッケージの高集
積化が増々進み、小型化どともに高信頼性が要求とれて
いる。こうした場合、アウターリード部からペレット塔
載部１狂の半＞９体素子までのパスが短くなり、パッケ
ージを構成する樹脂のみの対応では気密性や耐湿性をは
かることが困難となっている。These platings were not done with consideration to the adhesion of the mold resin forming the plastic package. Now, with the advancement of 111ST and VISI, packages are becoming more and more highly integrated, and there is a demand for smaller size and higher reliability. In such a case, the path from the outer lead part to the pellet loading part to the half-nine element is shortened, making it difficult to achieve airtightness and moisture resistance using only the resin that constitutes the package.
本発明は」一連の事情に基づいてなされたもので、イン
ナーリード部とモールド樹脂との密着ｖ１をよくしモー
ルド樹脂Ｗ面から侵入して半導体素子に悪影響を与える
水分をしゃ断することによりモールド樹脂製品の耐湿性
の向上をπ］す、信頼性の高い製品を供給することので
きるリードフレームを提供することを目的とする。The present invention was made based on a series of circumstances, and improves the adhesion v1 between the inner lead part and the mold resin, and blocks moisture that enters from the mold resin W surface and adversely affects the semiconductor element. The purpose of the present invention is to provide a lead frame that can improve the moisture resistance of the product and provide a highly reliable product.
上記［］的を達成するため本発明は、ペレット塔載部ど
、この塔載部に近接しパッケージに封入されたインナー
リード部おにびこのパッケージ外に突出するアウターリ
ード部から成るリードとを有゛す゛るリードフレームに
おいて、インナーリードの表面を粗く加工し、アウター
リード部を密に加工するか、あるいはインナーリード部
表面のみに所望の９ざのメッキ層を設けることを特徴と
するリードフレームを提供づるものである。In order to achieve the above object [], the present invention provides a lead consisting of an inner lead part enclosed in a package adjacent to the pellet tower part, etc., and an outer lead part protruding outside the package. Among the existing lead frames, there is one in which the surface of the inner lead is roughened and the outer lead part is processed densely, or the desired nine plating layers are provided only on the surface of the inner lead part. This is what we provide.
以−ト、添付図面の第２図乃至第４図を参照して本発明
のいくつかの実施例を説明する。第３図および第１図は
この発明の実施例に係るプラスチックパッケージの断面
図を示したものである。なお、第２図は従来のリードフ
レームを用いたパッケージの断面図であるが、これと対
比しながらこの発明の詳細な説明する。Some embodiments of the present invention will now be described with reference to FIGS. 2 to 4 of the accompanying drawings. FIG. 3 and FIG. 1 show cross-sectional views of a plastic package according to an embodiment of the present invention. Note that FIG. 2 is a cross-sectional view of a package using a conventional lead frame, and the present invention will be explained in detail in comparison with this.
一般にモールド樹脂とリードフレームとの間の密着性は
リードフレームの材質または表面粗さに依存する点が多
い。そしてリードフレームの表面粗さを粗くすれば密着
性は良り、表面粗さを密にすれば密着性は悪くなる。Generally, the adhesion between a mold resin and a lead frame depends in many ways on the material or surface roughness of the lead frame. If the surface roughness of the lead frame is roughened, the adhesion will be good, and if the surface roughness is made dense, the adhesion will be bad.
そこでパッケージ内に収納される半導体素子の耐湿性の
面から考慮すると、インナーリード部の密着性は良くし
、樹脂封止後のモールド樹脂のパリを取りやすくする点
から考えるとアウターリード部の密着性は悪い方が良い
。Therefore, from the viewpoint of moisture resistance of the semiconductor element housed in the package, the adhesion of the inner lead part should be good, and from the point of view of making it easier to remove the flakes from the mold resin after resin sealing, the adhesion of the outer lead part should be good. The worse the gender, the better.
そこでこの２つの要求を同時に満２．するようにリード
フレームの表面を加工すれば良いことになる。従来の全
面メッキの方法ではメツ４：面とモールド樹脂どの密着
性が良い場合には、半導体素子の耐湿性は良くなるがパ
リが付着しやすくなり、その逆の場合にはパリは付着し
にくくなるが耐湿性が悪くなる。Therefore, these two requirements can be met at the same time. All you have to do is process the surface of the lead frame so that it does. In the conventional full-surface plating method, 4: If the adhesion between the surface and the mold resin is good, the moisture resistance of the semiconductor element will be good, but it will be easy for Paris to adhere, and vice versa, it will be difficult for Paris to adhere. However, moisture resistance deteriorates.
また部分メッキの場合には、メッキ面の密着性が良い場
合でもメッキは部分的にしかおこなわれていないため、
インナーリード部の密４１１と’Ｅ−ルド樹脂のパリ付
着性の問題とを同時に満足させることはできない。In addition, in the case of partial plating, even if the adhesion of the plated surface is good, the plating is only partially applied.
It is not possible to simultaneously satisfy the problem of the density of the inner lead portion (411) and the adhesiveness of the 'E-old resin.
ざらに現在おこなわれている部分メッキ法はリードフレ
ームの素子塔載部１付近の表面のみに施されており、裏
面の密着性は必ずしも良くなかった。The currently used partial plating method is applied only to the surface of the lead frame in the vicinity of the element mounting portion 1, and the adhesion on the back surface is not necessarily good.
第２図に示すメッキ部６が従来おこなわれていた部分メ
ッキ部である。そこでこの発明ではまずインナーリード
部の密着ｉ（［を良くするために、第３図に示すように
リード２のインナーリード部２ｂの部分のみをラップま
たはプレス等で素材の表面粗ざを相＜−Ｊ’る。素材ど
しては現在一般に使用されている表面粗さ±０．５ 程
度の４２７０イ銅系合金を用いれば良い。また第４図に
示すようにインナーリード部２ｂのみにメッキ層７を付
着して別祠質にしても良い。次いでアウターリード部２
ａの密着性を悪くしてモールド樹脂のパリを付着しに＜
＜シパリ取りを容易にするために、アラターリード部２
ａの表面粗さは密な材質を使用する。表面粗さの目安と
して０．５８以下のものを用いればＪ：い。The plating section 6 shown in FIG. 2 is a conventional partial plating section. Therefore, in this invention, first, in order to improve the adhesion i of the inner lead part, as shown in FIG. -J'.As for the material, 4270-I copper alloy, which is currently commonly used and has a surface roughness of approximately ±0.5, may be used.Also, as shown in Fig. 4, only the inner lead portion 2b is plated. The layer 7 may be attached to form a separate layer.Then, the outer lead portion 2
In order to reduce the adhesion of a and adhere the mold resin.
<In order to make it easier to remove the shimari, the outer lead part 2
For the surface roughness of a, a dense material is used. If a surface roughness of 0.58 or less is used as a guideline, J: Yes.
また素材どして表面粗さが粗いものを使用した場合には
、アウターリード部２ａのみをラップまたはメッキ処理
して密着性を悪くする等の処理を施しても良い。Further, when a material with a rough surface is used, only the outer lead portion 2a may be subjected to a treatment such as lapping or plating to deteriorate adhesion.
なお、第３図に示１−にうに表面粗ざを粗くしたインナ
ーリード部２ｂ上の部分メッキ層６を“同時に施すよう
に構成して−ｔＪＪ：い。It should be noted that the partial plating layer 6 on the inner lead portion 2b having a roughened surface as shown in FIG. 3 is configured to be applied simultaneously.
この場合には半導体索子８とペレット搭載部１とのダイ
ボンドが容易になるだけでなく、半導体素子８とリード
２どの間のワイヤーボンドも容易になるという利点があ
る。In this case, there is an advantage that not only the die bonding between the semiconductor cable 8 and the pellet mounting portion 1 is facilitated, but also the wire bonding between the semiconductor element 8 and any of the leads 2 is facilitated.
なお符号９はボンディングワイＡ７を、符１０はダイボ
ンド用樹脂たとえば金シリコン等をそれぞれ示したもの
である。なお表面粗さの加工やメッキ処理はリード２の
表、裏、表面いずれでも可能であるが、両面に施すこと
によりその効果は大きくなる。Note that the reference numeral 9 indicates bonding wire A7, and the reference numeral 10 indicates a resin for die bonding, such as gold silicon. The surface roughening process and plating process can be performed on either the front, back, or front side of the lead 2, but the effect will be greater if it is applied to both sides.
上記の如く本発明によれば、リードフレーｌ＼とどモー
ルド樹脂どの密着性を考慮してアウターリード部とイン
ナーリード部とではその表面粗さを異るようにしたり、
表面祠買を異なるように構成したので、パッケージ内に
収納させる半導体素子に対する耐洞性の向上を図ること
ができるとともに、モールド樹脂のパリ取りが容易にな
り、外装メッキ＋１が良くなるリードフレームを１ｑる
ことができる。As described above, according to the present invention, the outer lead portion and the inner lead portion are made to have different surface roughness in consideration of the adhesion between the lead frame and the mold resin.
Since the surface abrasions are configured differently, it is possible to improve the cavitation resistance for the semiconductor elements housed in the package, and also to make it easier to remove the mold resin and create a lead frame with better exterior plating +1. 1q is possible.
第１図は従来使用されているリードフレームの構造を示
す平面図、第２図は従来のリードフレームを用いた半導
体装置の断面図、第３図および第４図は本発明の実施例
に係る半導体装置の断面図である。
１・・・ペレット搭載部、２・・・リード、２ａ・・・
アウターリード部、２ｂ・・・インナーリード部、７・
・・メッキ層、８・・・半導体素子
出願人代理人 猪 設 清FIG. 1 is a plan view showing the structure of a conventionally used lead frame, FIG. 2 is a sectional view of a semiconductor device using a conventional lead frame, and FIGS. 3 and 4 are according to embodiments of the present invention. FIG. 2 is a cross-sectional view of a semiconductor device. 1... Pellet mounting part, 2... Lead, 2a...
Outer lead part, 2b... Inner lead part, 7.
...Plating layer, 8...Semiconductor device applicant's agent Kiyoshi Inose
Claims (1)
パッケージ内に封入されるインナーリード部およびこの
パッケージ外に突出するアウターリード部からなる複数
のリードとを有するリードフレームにおいて、前記イン
ナーリード部の表面は粗く加工され、アウタリード部の
表面は密に加工されることを特徴とするり一もドフレー
ム。 ２ ペレット塔載部と、このペレット塔載部に近接しパ
ッケージ内に封入されるインナーリード部およびこのパ
ッケージ外に突出するアウターリード部からなる複数の
リードとを有するリードフレームにおいて、前記インナ
ーリード部の表面のみに所望の厚さのメッキ層を形成し
たことを特徴とするリードフレーム。[Claims] 1. A lead frame having a pellet loading part, and a plurality of leads including an inner lead part that is close to the pellet 1h loading part and is enclosed in a package, and an outer lead part that projects outside the package. 2. A single-lead frame characterized in that the surface of the inner lead portion is rough-processed, and the surface of the outer lead portion is densely processed. 2. In a lead frame having a pellet tower mounting part, a plurality of leads consisting of an inner lead part that is close to the pellet tower mounting part and is enclosed in a package, and an outer lead part that projects outside the package, the inner lead part A lead frame characterized in that a plating layer of a desired thickness is formed only on the surface of the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59088165A JPS60231349A (en) | 1984-05-01 | 1984-05-01 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59088165A JPS60231349A (en) | 1984-05-01 | 1984-05-01 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60231349A true JPS60231349A (en) | 1985-11-16 |
Family
ID=13935309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59088165A Pending JPS60231349A (en) | 1984-05-01 | 1984-05-01 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60231349A (en) |
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| US6002173A (en) * | 1991-12-20 | 1999-12-14 | Sgs-Thomson Microelectronics S.R.L. | Semiconductor device package with metal-polymer joint of controlled roughness |
| WO1999067821A1 (en) * | 1998-06-24 | 1999-12-29 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
| EP0867935A3 (en) * | 1997-03-25 | 2000-03-15 | Mitsui Chemicals, Inc. | Plastic package, semiconductor device, and method of manufacturing plastic package |
| KR100286694B1 (en) * | 1998-03-12 | 2001-04-16 | 최현두 | Crystal oscillator |
| US6608366B1 (en) | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
| US6627977B1 (en) | 2002-05-09 | 2003-09-30 | Amkor Technology, Inc. | Semiconductor package including isolated ring structure |
| US6700187B2 (en) | 2001-03-27 | 2004-03-02 | Amkor Technology, Inc. | Semiconductor package and method for manufacturing the same |
| US6825062B2 (en) | 1998-11-20 | 2004-11-30 | Amkor Technology, Inc. | Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant |
| US6833609B1 (en) | 1999-11-05 | 2004-12-21 | Amkor Technology, Inc. | Integrated circuit device packages and substrates for making the packages |
| US6841414B1 (en) | 2002-06-19 | 2005-01-11 | Amkor Technology, Inc. | Saw and etch singulation method for a chip package |
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| US6867071B1 (en) | 2002-07-12 | 2005-03-15 | Amkor Technology, Inc. | Leadframe including corner leads and semiconductor package using same |
| CN101887877A (en) * | 2009-05-13 | 2010-11-17 | 日立电线精密株式会社 | Lead frame, semiconductor device and manufacturing method of the lead frame |
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| US7906855B1 (en) | 2008-01-21 | 2011-03-15 | Amkor Technology, Inc. | Stacked semiconductor package and method of making same |
| US8072050B1 (en) | 2008-11-18 | 2011-12-06 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including passive device |
| US8154111B2 (en) | 1999-12-16 | 2012-04-10 | Amkor Technology, Inc. | Near chip size semiconductor package |
| US8691632B1 (en) | 2002-11-08 | 2014-04-08 | Amkor Technology, Inc. | Wafer level package and fabrication method |
| US8866278B1 (en) | 2011-10-10 | 2014-10-21 | Amkor Technology, Inc. | Semiconductor device with increased I/O configuration |
| US8900995B1 (en) | 2010-10-05 | 2014-12-02 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
| US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
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-
1984
- 1984-05-01 JP JP59088165A patent/JPS60231349A/en active Pending
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|---|---|---|---|---|
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| EP0867935A3 (en) * | 1997-03-25 | 2000-03-15 | Mitsui Chemicals, Inc. | Plastic package, semiconductor device, and method of manufacturing plastic package |
| KR100286694B1 (en) * | 1998-03-12 | 2001-04-16 | 최현두 | Crystal oscillator |
| US8853836B1 (en) | 1998-06-24 | 2014-10-07 | Amkor Technology, Inc. | Integrated circuit package and method of making the same |
| WO1999067821A1 (en) * | 1998-06-24 | 1999-12-29 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
| US9224676B1 (en) | 1998-06-24 | 2015-12-29 | Amkor Technology, Inc. | Integrated circuit package and method of making the same |
| US6630728B2 (en) | 1998-06-24 | 2003-10-07 | Amkor Technology, Inc. | Plastic integrated circuit package and leadframe for making the package |
| US8963301B1 (en) | 1998-06-24 | 2015-02-24 | Amkor Technology, Inc. | Integrated circuit package and method of making the same |
| US6825062B2 (en) | 1998-11-20 | 2004-11-30 | Amkor Technology, Inc. | Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant |
| US6833609B1 (en) | 1999-11-05 | 2004-12-21 | Amkor Technology, Inc. | Integrated circuit device packages and substrates for making the packages |
| US8154111B2 (en) | 1999-12-16 | 2012-04-10 | Amkor Technology, Inc. | Near chip size semiconductor package |
| US9362210B2 (en) | 2000-04-27 | 2016-06-07 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
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| US6608366B1 (en) | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
| US6627977B1 (en) | 2002-05-09 | 2003-09-30 | Amkor Technology, Inc. | Semiconductor package including isolated ring structure |
| US6841414B1 (en) | 2002-06-19 | 2005-01-11 | Amkor Technology, Inc. | Saw and etch singulation method for a chip package |
| US6867071B1 (en) | 2002-07-12 | 2005-03-15 | Amkor Technology, Inc. | Leadframe including corner leads and semiconductor package using same |
| US8691632B1 (en) | 2002-11-08 | 2014-04-08 | Amkor Technology, Inc. | Wafer level package and fabrication method |
| US10665567B1 (en) | 2002-11-08 | 2020-05-26 | Amkor Technology, Inc. | Wafer level package and fabrication method |
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| US8952522B1 (en) | 2002-11-08 | 2015-02-10 | Amkor Technology, Inc. | Wafer level package and fabrication method |
| US6847099B1 (en) | 2003-02-05 | 2005-01-25 | Amkor Technology Inc. | Offset etched corner leads for semiconductor package |
| US7872343B1 (en) | 2007-08-07 | 2011-01-18 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
| US7906855B1 (en) | 2008-01-21 | 2011-03-15 | Amkor Technology, Inc. | Stacked semiconductor package and method of making same |
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| US10811341B2 (en) | 2009-01-05 | 2020-10-20 | Amkor Technology Singapore Holding Pte Ltd. | Semiconductor device with through-mold via |
| US11869829B2 (en) | 2009-01-05 | 2024-01-09 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device with through-mold via |
| JP2010267730A (en) * | 2009-05-13 | 2010-11-25 | Hitachi Cable Precision Co Ltd | Lead frame, semiconductor device and method of manufacturing the lead frame |
| CN101887877A (en) * | 2009-05-13 | 2010-11-17 | 日立电线精密株式会社 | Lead frame, semiconductor device and manufacturing method of the lead frame |
| US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
| US10546833B2 (en) | 2009-12-07 | 2020-01-28 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
| US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
| US9324614B1 (en) | 2010-04-06 | 2016-04-26 | Amkor Technology, Inc. | Through via nub reveal method and structure |
| US9159672B1 (en) | 2010-08-02 | 2015-10-13 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
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